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Commit 772d274

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Fix the usart rw order bug
1 parent 20af32e commit 772d274

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1 file changed

+24
-16
lines changed

1 file changed

+24
-16
lines changed

qiling/hw/char/stm32f4xx_usart.py

Lines changed: 24 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,8 @@ def __init__(self, ql, label, intn=None):
6060
self.send_buf = bytearray()
6161

6262
def read(self, offset: int, size: int) -> int:
63+
self.ql.log.debug(f'[{self.label.upper()}] [R] {self.find_field(offset, size):10s}')
64+
6365
buf = ctypes.create_string_buffer(size)
6466
ctypes.memmove(buf, ctypes.addressof(self.usart) + offset, size)
6567
retval = int.from_bytes(buf.raw, byteorder='little')
@@ -70,25 +72,37 @@ def read(self, offset: int, size: int) -> int:
7072
return retval
7173

7274
def write(self, offset: int, size: int, value: int):
75+
self.ql.log.debug(f'[{self.label.upper()}] [W] {self.find_field(offset, size):10s} = {hex(value)}')
76+
7377
if offset == self.struct.SR.offset:
7478
self.usart.SR &= value | USART_SR.CTS | USART_SR.LBD | USART_SR.TC | USART_SR.RXNE
7579

7680
elif offset == self.struct.DR.offset:
77-
self.transfer(value & 0xff)
78-
self.usart.SR |= USART_SR.TC
81+
self.usart.SR &= ~USART_SR.TXE
82+
self.usart.DR = value
7983

8084
else:
8185
data = (value).to_bytes(size, byteorder='little')
8286
ctypes.memmove(ctypes.addressof(self.usart) + offset, data, size)
8387

84-
def transfer(self, value: int):
85-
""" transfer data to buffer
86-
87-
Args:
88-
value (int): transfer data
88+
def transfer(self):
89+
""" transfer data from DR to shift buffer and
90+
receive data from user buffer into DR
8991
"""
90-
self.send_buf.append(value)
91-
self.ql.log.debug(f'[{self.label}] Send {repr(chr(value))}')
92+
93+
if not (self.usart.SR & USART_SR.TXE):
94+
data = self.usart.DR
95+
96+
self.usart.SR |= USART_SR.TXE
97+
self.send_buf.append(data)
98+
self.ql.log.debug(f'[{self.label}] Send {repr(chr(data))}')
99+
100+
if not (self.usart.SR & USART_SR.RXNE):
101+
# TXE bit must had been cleared
102+
if self.recv_buf:
103+
self.usart.SR |= USART_SR.RXNE
104+
self.usart.DR = self.recv_buf.pop(0)
105+
92106

93107
def send(self, data: bytes):
94108
""" send user data into USART.
@@ -109,13 +123,7 @@ def recv(self) -> bytes:
109123
return data
110124

111125
def step(self):
112-
if not (self.usart.SR & USART_SR.RXNE):
113-
if self.recv_buf:
114-
self.usart.SR |= USART_SR.RXNE
115-
self.usart.DR = self.recv_buf.pop(0)
116-
117-
if not (self.usart.SR & USART_SR.TXE):
118-
self.usart.SR |= USART_SR.TXE
126+
self.transfer()
119127

120128
if self.intn is not None:
121129
if (self.usart.CR1 & USART_CR1.PEIE and self.usart.SR & USART_SR.PE) or \

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