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Merge pull request #616 from learn-more/disasm_format
Update disasm to include module name, only create the disassembler once
2 parents f85da96 + cd3a593 commit 77fa982

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+12
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1 file changed

+12
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qiling/os/utils.py

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,7 @@ def __init__(self, ql):
124124
self.ql = ql
125125
self.path = None
126126
self.output_ready = False
127+
self.md = None
127128

128129
def lsbmsb_convert(self, sc, size=4):
129130
split_bytes = []
@@ -231,15 +232,23 @@ def restore(ql):
231232
# we want to rewrite the return address to the function
232233
self.ql.stack_write(0, start)
233234

235+
def get_offset_and_name(self, addr):
236+
for begin, end, access, name in self.ql.mem.map_info:
237+
if begin <= addr and end > addr:
238+
return addr-begin, name
239+
return addr, '-'
240+
234241
def disassembler(self, ql, address, size):
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tmp = self.ql.mem.read(address, size)
236243

237-
md = self.ql.create_disassembler()
244+
if not self.md:
245+
self.md = self.ql.create_disassembler()
238246

239-
insn = md.disasm(tmp, address)
247+
insn = self.md.disasm(tmp, address)
240248
opsize = int(size)
241249

242-
log_data = ("0x%x" % (address)).ljust( (self.ql.archbit // 8) + 15)
250+
offset, name = self.get_offset_and_name(address)
251+
log_data = '0x%0*x {%-20s + 0x%06x} ' % (self.ql.archbit // 4, address, name, offset)
243252

244253
temp_str = ""
245254
for i in tmp:

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