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Merge branch 'qilingframework:dev' into dev
2 parents dd20546 + 2e782b1 commit 96749b0

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lines changed

‎qiling/hw/char/__init__.py‎

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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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6-
from .stm32f4xx_usart import STM32F4xxUsart
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from .stm32f4xx_usart import STM32F4xxUsart
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from .gd32vf1xx_usart import GD32VF1xxUsart

‎qiling/hw/char/gd32vf1xx_usart.py‎

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import ctypes
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from qiling.hw.connectivity import QlConnectivityPeripheral
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class GD32VF1xxUsart(QlConnectivityPeripheral):
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class Type(ctypes.Structure):
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""" Universal synchronous asynchronous receiver
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transmitter
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"""
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_fields_ = [
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("STAT", ctypes.c_uint32), # Address offset: 0x00, Status register
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("DATA", ctypes.c_uint32), # Address offset: 0x04, Data register
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("BAUD", ctypes.c_uint32), # Address offset: 0x08, Baud rate register
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("CTL0", ctypes.c_uint32), # Address offset: 0x0C, Control register 0
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("CTL1", ctypes.c_uint32), # Address offset: 0x10, Control register 1
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("CTL2", ctypes.c_uint32), # Address offset: 0x14, Control register 2
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("GP" , ctypes.c_uint32), # Address offset: 0x18, Guard time and prescaler register
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]
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def __init__(self, ql, label):
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super().__init__(ql, label)
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self.usart = self.struct(
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STAT = 0x000000c0,
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DATA = 0x00000000,
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BAUD = 0x00000000,
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CTL0 = 0x00000000,
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CTL1 = 0x00000000,
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CTL2 = 0x00000000,
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GP = 0x00000000,
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)
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@QlConnectivityPeripheral.device_handler
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def step(self):
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pass

‎qiling/hw/const/gd32vf1xx_dma_const.py‎

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from enum import IntEnum
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class INTF(IntEnum):
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GIF0 = 0x1 << 0 # Global interrupt flag of channel 0
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FTFIF0 = 0x1 << 1 # Full Transfer finish flag of channe 0
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HTFIF0 = 0x1 << 2 # Half transfer finish flag of channel 0
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ERRIF0 = 0x1 << 3 # Error flag of channel 0
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GIF1 = 0x1 << 4 # Global interrupt flag of channel 1
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FTFIF1 = 0x1 << 5 # Full Transfer finish flag of channe 1
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HTFIF1 = 0x1 << 6 # Half transfer finish flag of channel 1
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ERRIF1 = 0x1 << 7 # Error flag of channel 1
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GIF2 = 0x1 << 8 # Global interrupt flag of channel 2
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FTFIF2 = 0x1 << 9 # Full Transfer finish flag of channe 2
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HTFIF2 = 0x1 << 10 # Half transfer finish flag of channel 2
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ERRIF2 = 0x1 << 11 # Error flag of channel 2
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GIF3 = 0x1 << 12 # Global interrupt flag of channel 3
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FTFIF3 = 0x1 << 13 # Full Transfer finish flag of channe 3
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HTFIF3 = 0x1 << 14 # Half transfer finish flag of channel 3
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ERRIF3 = 0x1 << 15 # Error flag of channel 3
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GIF4 = 0x1 << 16 # Global interrupt flag of channel 4
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FTFIF4 = 0x1 << 17 # Full Transfer finish flag of channe 4
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HTFIF4 = 0x1 << 18 # Half transfer finish flag of channel 4
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ERRIF4 = 0x1 << 19 # Error flag of channel 4
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GIF5 = 0x1 << 20 # Global interrupt flag of channel 5
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FTFIF5 = 0x1 << 21 # Full Transfer finish flag of channe 5
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HTFIF5 = 0x1 << 22 # Half transfer finish flag of channel 5
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ERRIF5 = 0x1 << 23 # Error flag of channel 5
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GIF6 = 0x1 << 24 # Global interrupt flag of channel 6
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FTFIF6 = 0x1 << 25 # Full Transfer finish flag of channe 6
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HTFIF6 = 0x1 << 26 # Half transfer finish flag of channel 6
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ERRIF6 = 0x1 << 27 # Error flag of channel 6
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class INTC(IntEnum):
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GIFC0 = 0x1 << 0 # Clear global interrupt flag of channel 0
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FTFIFC0 = 0x1 << 1 # Clear bit for full transfer finish flag of channel 0
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HTFIFC0 = 0x1 << 2 # Clear bit for half transfer finish flag of channel 0
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ERRIFC0 = 0x1 << 3 # Clear bit for error flag of channel 0
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GIFC1 = 0x1 << 4 # Clear global interrupt flag of channel 1
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FTFIFC1 = 0x1 << 5 # Clear bit for full transfer finish flag of channel 1
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HTFIFC1 = 0x1 << 6 # Clear bit for half transfer finish flag of channel 1
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ERRIFC1 = 0x1 << 7 # Clear bit for error flag of channel 1
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GIFC2 = 0x1 << 8 # Clear global interrupt flag of channel 2
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FTFIFC2 = 0x1 << 9 # Clear bit for full transfer finish flag of channel 2
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HTFIFC2 = 0x1 << 10 # Clear bit for half transfer finish flag of channel 2
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ERRIFC2 = 0x1 << 11 # Clear bit for error flag of channel 2
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GIFC3 = 0x1 << 12 # Clear global interrupt flag of channel 3
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FTFIFC3 = 0x1 << 13 # Clear bit for full transfer finish flag of channel 3
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HTFIFC3 = 0x1 << 14 # Clear bit for half transfer finish flag of channel 3
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ERRIFC3 = 0x1 << 15 # Clear bit for error flag of channel 3
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GIFC4 = 0x1 << 16 # Clear global interrupt flag of channel 4
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FTFIFC4 = 0x1 << 17 # Clear bit for full transfer finish flag of channel 4
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HTFIFC4 = 0x1 << 18 # Clear bit for half transfer finish flag of channel 4
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ERRIFC4 = 0x1 << 19 # Clear bit for error flag of channel 4
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GIFC5 = 0x1 << 20 # Clear global interrupt flag of channel 5
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FTFIFC5 = 0x1 << 21 # Clear bit for full transfer finish flag of channel 5
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HTFIFC5 = 0x1 << 22 # Clear bit for half transfer finish flag of channel 5
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ERRIFC5 = 0x1 << 23 # Clear bit for error flag of channel 5
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GIFC6 = 0x1 << 24 # Clear global interrupt flag of channel 6
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FTFIFC6 = 0x1 << 25 # Clear bit for full transfer finish flag of channel 6
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HTFIFC6 = 0x1 << 26 # Clear bit for half transfer finish flag of channel 6
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ERRIFC6 = 0x1 << 27 # Clear bit for error flag of channel 6
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class CH0CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH0CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH0PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH0MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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class CH1CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH1CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH1PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH1MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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class CH2CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH2CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH2PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH2MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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class CH3CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH3CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH3PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH3MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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class CH4CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH4CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH4PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH4MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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class CH5CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH5CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH5PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH5MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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class CH6CTL(IntEnum):
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CHEN = 0x1 << 0 # Channel enable
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FTFIE = 0x1 << 1 # Enable bit for channel full transfer finish interrupt
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HTFIE = 0x1 << 2 # Enable bit for channel half transfer finish interrupt
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ERRIE = 0x1 << 3 # Enable bit for channel error interrupt
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DIR = 0x1 << 4 # Transfer direction
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CMEN = 0x1 << 5 # Circular mode enable
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PNAGA = 0x1 << 6 # Next address generation algorithm of peripheral
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MNAGA = 0x1 << 7 # Next address generation algorithm of memory
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PWIDTH = 0x3 << 8 # Transfer data size of peripheral
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MWIDTH = 0x3 << 10 # Transfer data size of memory
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PRIO = 0x3 << 12 # Priority level
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M2M = 0x1 << 14 # Memory to Memory Mode
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class CH6CNT(IntEnum):
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CNT = 0xffff << 0 # Transfer counter
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class CH6PADDR(IntEnum):
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PADDR = 0xffffffff << 0 # Peripheral base address
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class CH6MADDR(IntEnum):
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MADDR = 0xffffffff << 0 # Memory base address
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‎qiling/hw/const/gd32vf1xx_i2c_const.py‎

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from enum import IntEnum
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class CTL0(IntEnum):
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SRESET = 0x1 << 15 # Software reset
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SALT = 0x1 << 13 # SMBus alert
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PECTRANS = 0x1 << 12 # PEC Transfer
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POAP = 0x1 << 11 # Position of ACK and PEC when receiving
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ACKEN = 0x1 << 10 # Whether or not to send an ACK
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STOP = 0x1 << 9 # Generate a STOP condition on I2C bus
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START = 0x1 << 8 # Generate a START condition on I2C bus
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SS = 0x1 << 7 # Whether to stretch SCL low when data is not ready in slave mode
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GCEN = 0x1 << 6 # Whether or not to response to a General Call (0x00)
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PECEN = 0x1 << 5 # PEC Calculation Switch
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ARPEN = 0x1 << 4 # ARP protocol in SMBus switch
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SMBSEL = 0x1 << 3 # SMBusType Selection
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SMBEN = 0x1 << 1 # SMBus/I2C mode switch
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I2CEN = 0x1 << 0 # I2C peripheral enable
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class CTL1(IntEnum):
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DMALST = 0x1 << 12 # Flag indicating DMA last transfer
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DMAON = 0x1 << 11 # DMA mode switch
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BUFIE = 0x1 << 10 # Buffer interrupt enable
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EVIE = 0x1 << 9 # Event interrupt enable
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ERRIE = 0x1 << 8 # Error interrupt enable
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I2CCLK = 0x3f << 0 # I2C Peripheral clock frequency
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class SADDR0(IntEnum):
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ADDFORMAT = 0x1 << 15 # Address mode for the I2C slave
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ADDRESS9_8 = 0x3 << 8 # Highest two bits of a 10-bit address
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ADDRESS7_1 = 0x7f << 1 # 7-bit address or bits 7:1 of a 10-bit address
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ADDRESS0 = 0x1 << 0 # Bit 0 of a 10-bit address
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class SADDR1(IntEnum):
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ADDRESS2 = 0x7f << 1 # Second I2C address for the slave in Dual-Address mode
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DUADEN = 0x1 << 0 # Dual-Address mode switch
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class DATA(IntEnum):
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TRB = 0xff << 0 # Transmission or reception data buffer register
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class STAT0(IntEnum):
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SMBALT = 0x1 << 15 # SMBus Alert status
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SMBTO = 0x1 << 14 # Timeout signal in SMBus mode
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PECERR = 0x1 << 12 # PEC error when receiving data
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OUERR = 0x1 << 11 # Over-run or under-run situation occurs in slave mode
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AERR = 0x1 << 10 # Acknowledge error
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LOSTARB = 0x1 << 9 # Arbitration Lost in master mode
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BERR = 0x1 << 8 # A bus error occurs indication a unexpected START or STOP condition on I2C bus
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TBE = 0x1 << 7 # I2C_DATA is Empty during transmitting
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RBNE = 0x1 << 6 # I2C_DATA is not Empty during receiving
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STPDET = 0x1 << 4 # STOP condition detected in slave mode
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ADD10SEND = 0x1 << 3 # Header of 10-bit address is sent in master mode
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BTC = 0x1 << 2 # Byte transmission completed
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ADDSEND = 0x1 << 1 # Address is sent in master mode or received and matches in slave mode
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SBSEND = 0x1 << 0 # START condition sent out in master mode
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class STAT1(IntEnum):
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PECV = 0xff << 8 # Packet Error Checking Value that calculated by hardware when PEC is enabled
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DUMODF = 0x1 << 7 # Dual Flag in slave mode
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HSTSMB = 0x1 << 6 # SMBus Host Header detected in slave mode
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DEFSMB = 0x1 << 5 # Default address of SMBusDevice
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RXGC = 0x1 << 4 # General call address (00h) received
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TR = 0x1 << 2 # Whether the I2C is a transmitter or a receiver
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I2CBSY = 0x1 << 1 # Busy flag
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MASTER = 0x1 << 0 # A flag indicating whether I2C block is in master or slave mode
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class CKCFG(IntEnum):
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FAST = 0x1 << 15 # I2C speed selection in master mode
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DTCY = 0x1 << 14 # Duty cycle in fast mode
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CLKC = 0xfff << 0 # I2C Clock control in master mode
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class RT(IntEnum):
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RISETIME = 0x3f << 0 # Maximum rise time in master mode
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