Merge pull request #977 from cla7aye15I4nd/dev

Avoid scanning the entire syscall table

Author: cla7aye15I4nd

examples/mcu/LCD1602A.txt

@@ -23,18 +23,7 @@
             "sp": UC_ARM_REG_SP, 
             "lr": UC_ARM_REG_LR,
             "pc": UC_ARM_REG_PC,
-            # cortex-M Special Register
-            "msp": UC_ARM_REG_MSP,
-            "psp": UC_ARM_REG_PSP,
-            "xpsr": UC_ARM_REG_XPSR,
-            "xpsr_nzcvqg": UC_ARM_REG_XPSR_NZCVQG,
-            "apsr": UC_ARM_REG_APSR,
-            "ipsr": UC_ARM_REG_IPSR,
-            "epsr": UC_ARM_REG_EPSR,
-            "primask": UC_ARM_REG_PRIMASK,
-            "faultmask": UC_ARM_REG_FAULTMASK,
-            "basepri": UC_ARM_REG_BASEPRI,
-            "control": UC_ARM_REG_CONTROL,
+            
             # CPSR needs to be at offset 25 for GDB, see https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gdb/arch/arm.h;h=fa589fd0582c0add627a068e6f4947a909c45e86;hb=HEAD#l34
             # The fp registers inbetween have become obsolete
             "f0": UC_ARM_REG_INVALID,
@@ -51,28 +40,3 @@
             "c13_c0_3": UC_ARM_REG_C13_C0_3,
             "fpexc": UC_ARM_REG_FPEXC,
 }
-
-class IRQ(IntEnum):
-    NMI = -14
-    HARD_FAULT = -13
-    MEMORY_MANAGEMENT_FAULT = -12
-    BUS_FAULT = -11
-    USAGE_FAULT = -10
-    SVCALL = -5
-    PENDSV = -2
-    SYSTICK = -1
-
-class CONTROL(IntEnum):
-    FPCA  = 0b100
-    SPSEL = 0b010
-    PRIV  = 0b001
-
-class EXC_RETURN(IntEnum):
-    MASK = 0xfffffff0
-    RETURN_SP   = 0b0100
-    RETURN_MODE = 0b1000
-
-class EXCP(IntEnum):
-    SWI = 2            # software interrupt
-    EXCEPTION_EXIT = 8 # Return from v7M exception
-    

qiling/arch/arm_const.py

@@ -13,7 +13,7 @@
 from qiling.exception import QlErrorNotImplemented
 
 from .arm import QlArchARM
-from .arm_const import IRQ, EXC_RETURN, CONTROL, EXCP
+from .cortex_m_const import IRQ, EXC_RETURN, CONTROL, EXCP, reg_map
 
 class QlInterruptContext(ContextDecorator):
     def __init__(self, ql):
@@ -61,6 +61,13 @@ class QlArchCORTEX_M(QlArchARM):
     def __init__(self, ql):
         super().__init__(ql)
 
+        reg_maps = (
+            reg_map,            
+        )
+
+        for reg_maper in reg_maps:
+            self.ql.reg.expand_mapping(reg_maper)
+
         def intr_cb(ql, intno):
             if intno == EXCP.SWI:
                 ql.hw.nvic.set_pending(IRQ.SVCALL)                    

qiling/arch/cortex_m.py

@@ -0,0 +1,65 @@
+#!/usr/bin/env python3
+# 
+# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
+#
+
+from unicorn.arm_const import *
+from enum import IntEnum
+
+reg_map = {
+    "r0": UC_ARM_REG_R0,
+    "r1": UC_ARM_REG_R1, 
+    "r2": UC_ARM_REG_R2,
+    "r3": UC_ARM_REG_R3, 
+    "r4": UC_ARM_REG_R4,
+    "r5": UC_ARM_REG_R5,
+    "r6": UC_ARM_REG_R6, 
+    "r7": UC_ARM_REG_R7, 
+    "r8": UC_ARM_REG_R8,
+    "r9": UC_ARM_REG_R9, 
+    "r10": UC_ARM_REG_R10, 
+    "r11": UC_ARM_REG_R11,
+    "r12": UC_ARM_REG_R12, 
+    "sp": UC_ARM_REG_SP, 
+    "lr": UC_ARM_REG_LR,
+    "pc": UC_ARM_REG_PC,
+
+    # cortex-M Special Register
+    "msp": UC_ARM_REG_MSP,
+    "psp": UC_ARM_REG_PSP,
+    "xpsr": UC_ARM_REG_XPSR,    
+    "apsr": UC_ARM_REG_APSR,
+    "ipsr": UC_ARM_REG_IPSR,
+    "epsr": UC_ARM_REG_EPSR,
+    "primask": UC_ARM_REG_PRIMASK,
+    "faultmask": UC_ARM_REG_FAULTMASK,
+    "basepri": UC_ARM_REG_BASEPRI,
+    "control": UC_ARM_REG_CONTROL,
+
+    "xpsr_nzcvqg": UC_ARM_REG_XPSR_NZCVQG,
+}
+
+class IRQ(IntEnum):
+    NMI = -14
+    HARD_FAULT = -13
+    MEMORY_MANAGEMENT_FAULT = -12
+    BUS_FAULT = -11
+    USAGE_FAULT = -10
+    SVCALL = -5
+    PENDSV = -2
+    SYSTICK = -1
+
+class CONTROL(IntEnum):
+    FPCA  = 0b100
+    SPSEL = 0b010
+    PRIV  = 0b001
+
+class EXC_RETURN(IntEnum):
+    MASK = 0xfffffff0
+    RETURN_SP   = 0b0100
+    RETURN_MODE = 0b1000
+
+class EXCP(IntEnum):
+    SWI = 2            # software interrupt
+    EXCEPTION_EXIT = 8 # Return from v7M exception
+    

qiling/arch/cortex_m_const.py

@@ -6,7 +6,6 @@
 import ctypes
 
 from qiling.hw.peripheral import QlPeripheral
-from qiling.arch.arm_const import IRQ
 
 
 class CortexM4Nvic(QlPeripheral):

qiling/hw/intc/cm4_nvic.py

@@ -7,7 +7,7 @@
 import ctypes
 
 from qiling.hw.peripheral import QlPeripheral
-from qiling.arch.arm_const import IRQ
+from qiling.arch.cortex_m_const import IRQ
 
 class CortexM4Scb(QlPeripheral):
     class Type(ctypes.Structure):

qiling/hw/misc/cm4_scb.py

@@ -4,7 +4,7 @@
 #
 
 import ctypes
-from qiling.arch.arm_const import IRQ
+from qiling.arch.cortex_m_const import IRQ
 from qiling.hw.peripheral import QlPeripheral
 from qiling.hw.const.cm4_systick import SYSTICK_CTRL