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slight adjust to prep debugger readyness for mcu
1 parent b6cf49a commit ac1e85e

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4 files changed

+39
-27
lines changed

4 files changed

+39
-27
lines changed

examples/mcu/stm32f4_hello_gpio.py renamed to examples/mcu/stm32f4_gdb_gpio.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
def test_mcu_gpio_stm32f411():
99
ql = Qiling(["../../examples/rootfs/mcu/stm32f411/hello_gpioA.hex"],
1010
archtype="cortex_m", profile="stm32f411", verbose=QL_VERBOSE.DEBUG)
11-
11+
ql.debugger = 'gdb:127.0.0.1:9998'
1212
ql.hw.create('usart2')
1313
ql.hw.create('rcc')
1414
ql.hw.create('gpioa')

‎qiling/core.py‎

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -694,33 +694,34 @@ def run(self, begin=None, end=None, timeout=0, count=0, code = None):
694694
self.timeout = timeout
695695
self.count = count
696696

697+
# init debugger
698+
if self._debugger != False and self._debugger != None:
699+
self._debugger = debugger_setup(self._debugger, self)
700+
701+
if self.archtype not in QL_ARCH_NONEOS and self.archtype not in QL_ARCH_HARDWARE:
702+
self.write_exit_trap()
703+
# patch binary
704+
self.__enable_bin_patch()
705+
706+
# emulate the binary
707+
self.os.run()
708+
697709
if self.archtype in QL_ARCH_NONEOS:
698710
if code == None:
699711
return self.arch.run(self._code)
700712
else:
701713
return self.arch.run(code)
702-
714+
703715
if self.archtype in QL_ARCH_HARDWARE:
704716
self.__enable_bin_patch()
705717
if self.count <= 0:
706718
self.count = -1
707-
return self.arch.run(count=self.count, end=self.exit_point)
708-
709-
self.write_exit_trap()
710-
711-
# init debugger
712-
if self._debugger != False and self._debugger != None:
713-
self._debugger = debugger_setup(self._debugger, self)
714-
715-
# patch binary
716-
self.__enable_bin_patch()
717-
718-
# emulate the binary
719-
self.os.run()
720-
719+
self.arch.run(count=self.count, end=self.exit_point)
720+
721721
# run debugger
722722
if self._debugger != False and self._debugger != None:
723723
self._debugger.run()
724+
724725

725726

726727
# patch code to memory address

‎qiling/debugger/gdb/gdb.py‎

Lines changed: 18 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -51,14 +51,20 @@ def __init__(self, ql: Qiling, ip: str = '127.0.01', port: int = 9999):
5151
self.ip = ip
5252
self.port = port
5353

54-
if ql.code:
54+
55+
if ql.archtype in QL_ARCH_HARDWARE:
56+
load_address = ql.loader.load_address
57+
exit_point = load_address + os.path.getsize(ql.path)
58+
elif ql.code:
5559
load_address = ql.os.entry_point
5660
exit_point = load_address + len(ql.code)
5761
else:
5862
load_address = ql.loader.load_address
5963
exit_point = load_address + os.path.getsize(ql.path)
6064

61-
if self.ql.ostype in (QL_OS.LINUX, QL_OS.FREEBSD) and not self.ql.code:
65+
if ql.archtype in QL_ARCH_HARDWARE:
66+
self.entry_point = ql.loader.entry_point
67+
elif self.ql.ostype in (QL_OS.LINUX, QL_OS.FREEBSD) and not self.ql.code:
6268
self.entry_point = self.ql.os.elf_entry
6369
else:
6470
self.entry_point = self.ql.os.entry_point
@@ -72,12 +78,13 @@ def __init__(self, ql: Qiling, ip: str = '127.0.01', port: int = 9999):
7278

7379
#Setup register tables, order of tables is important
7480
self.tables = {
75-
QL_ARCH.A8086 : list({**x86_reg_map_16, **x86_reg_map_misc}.keys()),
76-
QL_ARCH.X86 : list({**x86_reg_map_32, **x86_reg_map_misc, **x86_reg_map_st}.keys()),
77-
QL_ARCH.X8664 : list({**x86_reg_map_64, **x86_reg_map_misc, **x86_reg_map_st}.keys()),
78-
QL_ARCH.ARM : list({**arm_reg_map}.keys()),
79-
QL_ARCH.ARM64 : list({**arm64_reg_map}.keys()),
80-
QL_ARCH.MIPS : list({**mips_reg_map}.keys()),
81+
QL_ARCH.A8086 : list({**x86_reg_map_16, **x86_reg_map_misc}.keys()),
82+
QL_ARCH.X86 : list({**x86_reg_map_32, **x86_reg_map_misc, **x86_reg_map_st}.keys()),
83+
QL_ARCH.X8664 : list({**x86_reg_map_64, **x86_reg_map_misc, **x86_reg_map_st}.keys()),
84+
QL_ARCH.ARM : list({**arm_reg_map}.keys()),
85+
QL_ARCH.CORTEX_M : list({**arm_reg_map}.keys()),
86+
QL_ARCH.ARM64 : list({**arm64_reg_map}.keys()),
87+
QL_ARCH.MIPS : list({**mips_reg_map}.keys()),
8188
}
8289

8390
def addr_to_str(self, addr: int, short: bool = False, endian: Literal['little', 'big'] = 'big') -> str:
@@ -168,6 +175,7 @@ def gdbqmark_converter(arch):
168175
QL_ARCH.X8664 : [ 0x06, 0x07, 0x10 ],
169176
QL_ARCH.MIPS : [ 0x1d, 0x00, 0x25 ],
170177
QL_ARCH.ARM : [ 0x0b, 0x0d, 0x0f ],
178+
QL_ARCH.CORTEX_M : [ 0x0b, 0x0d, 0x0f ],
171179
QL_ARCH.ARM64 : [ 0x1d, 0xf1, 0x20 ]
172180
}
173181
return adapter.get(arch)
@@ -498,7 +506,7 @@ def handle_q(subcmd):
498506

499507

500508
elif subcmd.startswith('Xfer:threads:read::0,'):
501-
if self.ql.ostype in QL_OS_NONPID:
509+
if self.ql.ostype in QL_OS_NONPID or self.ql.archtype in QL_ARCH_HARDWARE:
502510
self.send("l")
503511
else:
504512
file_contents = ("<threads>\r\n<thread id=\""+ str(self.ql.os.pid) + "\" core=\"1\" name=\"" + self.ql.targetname + "\"/>\r\n</threads>")
@@ -613,7 +621,7 @@ def handle_v(subcmd):
613621
self.send("")
614622

615623
elif subcmd.startswith('File:open'):
616-
if self.ql.ostype == QL_OS.UEFI:
624+
if self.ql.ostype == QL_OS.UEFI or self.ql.archtype in QL_ARCH_HARDWARE:
617625
self.send("F-1")
618626
return
619627

‎qiling/debugger/gdb/utils.py‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,10 @@ def __init__(self):
2626

2727
def initialize(self, ql, hook_address, exit_point=None, mappings=None):
2828
self.ql = ql
29-
self.current_address = self.entry_point = self.ql.os.entry_point
29+
if self.ql.archtype in QL_ARCH_HARDWARE:
30+
self.current_address = self.entry_point
31+
else:
32+
self.current_address = self.entry_point = self.ql.os.entry_point
3033
self.exit_point = exit_point
3134
self.mapping = mappings
3235
self._tmp_hook = self.ql.hook_address(self.entry_point_hook, hook_address)

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