22
33# More info, please refer to https://github.com/qilingframework/qiling/pull/765
44
5-
65from collections import deque
76from typing import Deque , Iterable , Iterator , Mapping , Tuple
87
9- from capstone import Cs , CsInsn , CS_OP_IMM , CS_OP_MEM , CS_OP_REG
8+ from capstone import Cs , CsInsn , CS_ARCH_X86 , CS_OP_IMM , CS_OP_MEM , CS_OP_REG
109from capstone .x86 import X86Op
1110from capstone .x86_const import X86_INS_LEA , X86_REG_INVALID , X86_REG_RIP
1211
1615
1716# <WORKAROUND>
1817def __uc2_workaround () -> Mapping [int , int ]:
19- """Starting from Unicron2, Unicron and Capstone Intel registers definitions are
18+ """Starting from Unicorn2, Unicorn and Capstone Intel registers definitions are
2019 no longer aligned and cannot be used interchangebly. This temporary workaround
2120 maps capstone x86 registers definitions to unicorn x86 registers definitions.
2221
@@ -47,6 +46,7 @@ def __get_trace_records(ql: Qiling, address: int, size: int, md: Cs) -> Iterator
4746 # unicorn denotes unsupported instructions by a magic size value. though these instructions
4847 # are not emulated, capstone can still parse them.
4948 if size == 0xf1f1f1f1 :
49+ # note that invalid instructions will generate a StopIteration exception here
5050 yield next (__get_trace_records (ql , address , 16 , md ))
5151 return
5252
@@ -125,6 +125,7 @@ def __parse_op(op: X86Op) -> str:
125125 2 : 'word' ,
126126 4 : 'dword' ,
127127 8 : 'qword' ,
128+ 10 : 'fword' ,
128129 16 : 'xmmword'
129130 }[op .size ]
130131
@@ -154,13 +155,15 @@ def enable_full_trace(ql: Qiling):
154155 md = ql .create_disassembler ()
155156 md .detail = True
156157
158+ assert md .arch == CS_ARCH_X86 , 'currently available only for intel architecture'
159+
157160 # if available, use symbols map to resolve memory accesses
158161 symsmap = getattr (ql .loader , 'symsmap' , {})
159162
160163 # show trace lines in a darker color so they would be easily distinguished from
161164 # ordinary log records
162- DarkGray = "\x1b [90m "
163- Default = "\x1b [39m "
165+ faded_color = "\033 [2m "
166+ reset_color = "\033 [0m "
164167
165168 def __trace_hook (ql : Qiling , address : int , size : int ):
166169 """[internal] Trace hook callback.
@@ -169,7 +172,7 @@ def __trace_hook(ql: Qiling, address: int, size: int):
169172 for record in __get_trace_records (ql , address , size , md ):
170173 line = __to_trace_line (record , symsmap )
171174
172- ql .log .debug (f'{ DarkGray } { line } { Default } ' )
175+ ql .log .debug (f'{ faded_color } { line } { reset_color } ' )
173176
174177 ql .hook_code (__trace_hook )
175178
@@ -189,6 +192,8 @@ def enable_history_trace(ql: Qiling, nrecords: int):
189192 md = ql .create_disassembler ()
190193 md .detail = True
191194
195+ assert md .arch == CS_ARCH_X86 , 'currently available only for intel architecture'
196+
192197 # if available, use symbols map to resolve memory accesses
193198 symsmap = getattr (ql .loader , 'symsmap' , {})
194199
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