Add missing ARM regs

Author: elicn

qiling/arch/arm.py

@@ -41,7 +41,11 @@ def uc(self) -> Uc:
 
     @cached_property
     def regs(self) -> QlRegisterManager:
-        regs_map = arm_const.reg_map
+        regs_map = dict(
+            **arm_const.reg_map,
+            **arm_const.reg_vfp
+        )
+
         pc_reg = 'pc'
         sp_reg = 'sp'