Add defualt float support

Author: cla7aye15I4nd

qiling/arch/riscv.py

@@ -17,7 +17,14 @@ class QlArchRISCV(QlArch):
     def __init__(self, ql: Qiling):
         super().__init__(ql)
 
-        self.ql.reg.expand_mapping(reg_map)
+        reg_maps = (
+            reg_map,
+            reg_csr_map,
+            reg_float_map,
+        )
+
+        for reg_maper in reg_maps:
+            self.ql.reg.expand_mapping(reg_maper)
         self.ql.reg.register_sp(reg_map["sp"])
         self.ql.reg.register_pc(reg_map["pc"])
 
@@ -34,3 +41,6 @@ def create_disassembler(self) -> Cs:
 
     def create_assembler(self) -> Ks:
         raise QlErrorNotImplemented("Keystone does not yet support riscv")
+
+    def enable_float(self):
+        self.ql.reg.mstatus = self.ql.reg.mstatus | MSTATUS.FS_DIRTY

qiling/arch/riscv64.py

@@ -8,19 +8,16 @@
 from keystone import Ks
 
 from qiling import Qiling
-from qiling.arch.arch import QlArch
 from qiling.arch.riscv_const import *
 from qiling.exception import QlErrorNotImplemented
 
+from .riscv import QlArchRISCV
 
-class QlArchRISCV64(QlArch):
+
+class QlArchRISCV64(QlArchRISCV):
     def __init__(self, ql: Qiling):
         super().__init__(ql)
 
-        self.ql.reg.expand_mapping(reg_map)
-        self.ql.reg.register_sp(reg_map["sp"])
-        self.ql.reg.register_pc(reg_map["pc"])
-
     # get initialized unicorn engine
     def get_init_uc(self) -> Uc:
         return Uc(UC_ARCH_RISCV, UC_MODE_RISCV64)

qiling/os/linux/linux.py

@@ -88,10 +88,12 @@ def load(self):
             self.thread_class = thread.QlLinuxX8664Thread     
 
         elif self.ql.archtype == QL_ARCH.RISCV:
+            self.ql.arch.enable_float()
             self.ql.hook_intno(self.hook_syscall, 8)
             self.thread_class = None
 
         elif self.ql.archtype == QL_ARCH.RISCV64:
+            self.ql.arch.enable_float()
             self.ql.hook_intno(self.hook_syscall, 8)
             self.thread_class = None