|
| 1 | +import ctypes |
| 2 | + |
| 3 | +from qiling.hw.connectivity import QlConnectivityPeripheral |
| 4 | + |
| 5 | + |
| 6 | +class GD32VF1xxI2c(QlConnectivityPeripheral): |
| 7 | + class Type(ctypes.Structure): |
| 8 | + """ Inter integrated circuit |
| 9 | + """ |
| 10 | + |
| 11 | + _fields_ = [ |
| 12 | + ("CTL0" , ctypes.c_uint16), # Address offset: 0x0, Control register 0 |
| 13 | + ("CTL1" , ctypes.c_uint16), # Address offset: 0x04, Control register 1 |
| 14 | + ("SADDR0", ctypes.c_uint16), # Address offset: 0x08, Slave address register 0 |
| 15 | + ("SADDR1", ctypes.c_uint16), # Address offset: 0x0C, Slave address register 1 |
| 16 | + ("DATA" , ctypes.c_uint16), # Address offset: 0x10, Transfer buffer register |
| 17 | + ("STAT0" , ctypes.c_uint16), # Address offset: 0x14, Transfer status register 0 |
| 18 | + ("STAT1" , ctypes.c_uint16), # Address offset: 0x18, Transfer status register 1 |
| 19 | + ("CKCFG" , ctypes.c_uint16), # Address offset: 0x1C, Clock configure register |
| 20 | + ("RT" , ctypes.c_uint16), # Address offset: 0x20, Rise time register |
| 21 | + ] |
| 22 | + |
| 23 | + def __init__(self, ql, label): |
| 24 | + super().__init__(ql, label) |
| 25 | + |
| 26 | + self.i2c = self.struct( |
| 27 | + CTL0 = 0x00000000, |
| 28 | + CTL1 = 0x00000000, |
| 29 | + SADDR0 = 0x00000000, |
| 30 | + SADDR1 = 0x00000000, |
| 31 | + DATA = 0x00000000, |
| 32 | + STAT0 = 0x00000000, |
| 33 | + STAT1 = 0x00000000, |
| 34 | + CKCFG = 0x00000000, |
| 35 | + RT = 0x00000002, |
| 36 | + ) |
| 37 | + |
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