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Add gd32 i2c component
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2 files changed

+39
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qiling/hw/i2c/__init__.py

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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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from .stm32f4xx_i2c import STM32F4xxI2c
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from .stm32f4xx_i2c import STM32F4xxI2c
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from .gd32vf1xx_i2c import GD32VF1xxI2c

qiling/hw/i2c/gd32vf1xx_i2c.py

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import ctypes
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from qiling.hw.connectivity import QlConnectivityPeripheral
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class GD32VF1xxI2c(QlConnectivityPeripheral):
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class Type(ctypes.Structure):
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""" Inter integrated circuit
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"""
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_fields_ = [
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("CTL0" , ctypes.c_uint16), # Address offset: 0x0, Control register 0
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("CTL1" , ctypes.c_uint16), # Address offset: 0x04, Control register 1
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("SADDR0", ctypes.c_uint16), # Address offset: 0x08, Slave address register 0
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("SADDR1", ctypes.c_uint16), # Address offset: 0x0C, Slave address register 1
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("DATA" , ctypes.c_uint16), # Address offset: 0x10, Transfer buffer register
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("STAT0" , ctypes.c_uint16), # Address offset: 0x14, Transfer status register 0
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("STAT1" , ctypes.c_uint16), # Address offset: 0x18, Transfer status register 1
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("CKCFG" , ctypes.c_uint16), # Address offset: 0x1C, Clock configure register
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("RT" , ctypes.c_uint16), # Address offset: 0x20, Rise time register
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]
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def __init__(self, ql, label):
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super().__init__(ql, label)
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self.i2c = self.struct(
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CTL0 = 0x00000000,
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CTL1 = 0x00000000,
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SADDR0 = 0x00000000,
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SADDR1 = 0x00000000,
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DATA = 0x00000000,
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STAT0 = 0x00000000,
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STAT1 = 0x00000000,
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CKCFG = 0x00000000,
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RT = 0x00000002,
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)
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