1+ {
2+ " ADC1 " {
3+ " base " 0x40012000,
4+ " struct " " STM32F4xxAdc" ,
5+ " type " " periperal"
6+ },
7+ " CRC " {
8+ " base " 0x40023000,
9+ " struct " " STM32F4xxCrc" ,
10+ " type " " periperal"
11+ },
12+ " DBGMCU " {
13+ " base " 0xe0042000,
14+ " struct " " STM32F4xxDbgmcu" ,
15+ " type " " periperal"
16+ },
17+ " DMA1 " {
18+ " base " 0x40026000,
19+ " struct " " STM32F4xxDma" ,
20+ " kwargs " {
21+ " stream0_intn " 11,
22+ " stream1_intn " 12,
23+ " stream2_intn " 13,
24+ " stream3_intn " 14,
25+ " stream4_intn " 15,
26+ " stream5_intn " 16,
27+ " stream6_intn " 17,
28+ " stream7_intn " 47
29+ },
30+ " type " " periperal"
31+ },
32+ " DMA2 " {
33+ " base " 0x40026400,
34+ " struct " " STM32F4xxDma" ,
35+ " kwargs " {
36+ " stream0_intn " 56,
37+ " stream1_intn " 57,
38+ " stream2_intn " 58,
39+ " stream3_intn " 59,
40+ " stream4_intn " 60,
41+ " stream5_intn " 68,
42+ " stream6_intn " 69,
43+ " stream7_intn " 70
44+ },
45+ " type " " periperal"
46+ },
47+ " EXTI " {
48+ " base " 0x40013c00,
49+ " struct " " STM32F4xxExti" ,
50+ " type " " periperal"
51+ },
52+ " FLASH " {
53+ " base " 0x8000000,
54+ " size " 0x80000,
55+ " type " " memory"
56+ },
57+ " FLASH OTP " {
58+ " base " 0x1fff7800,
59+ " size " 0x400,
60+ " type " " memory"
61+ },
62+ " GPIOA " {
63+ " base " 0x40020000,
64+ " struct " " STM32F4xxGpio" ,
65+ " type " " periperal"
66+ },
67+ " GPIOB " {
68+ " base " 0x40020400,
69+ " struct " " STM32F4xxGpio" ,
70+ " type " " periperal"
71+ },
72+ " GPIOC " {
73+ " base " 0x40020800,
74+ " struct " " STM32F4xxGpio" ,
75+ " type " " periperal"
76+ },
77+ " GPIOD " {
78+ " base " 0x40020c00,
79+ " struct " " STM32F4xxGpio" ,
80+ " type " " periperal"
81+ },
82+ " GPIOE " {
83+ " base " 0x40021000,
84+ " struct " " STM32F4xxGpio" ,
85+ " type " " periperal"
86+ },
87+ " GPIOH " {
88+ " base " 0x40021c00,
89+ " struct " " STM32F4xxGpio" ,
90+ " type " " periperal"
91+ },
92+ " I2C1 " {
93+ " base " 0x40005400,
94+ " struct " " STM32F4xxI2c" ,
95+ " kwargs " {
96+ " er_intn " 32,
97+ " ev_intn " 31
98+ },
99+ " type " " periperal"
100+ },
101+ " I2C2 " {
102+ " base " 0x40005800,
103+ " struct " " STM32F4xxI2c" ,
104+ " kwargs " {
105+ " er_intn " 34,
106+ " ev_intn " 33
107+ },
108+ " type " " periperal"
109+ },
110+ " I2C3 " {
111+ " base " 0x40005c00,
112+ " struct " " STM32F4xxI2c" ,
113+ " kwargs " {
114+ " er_intn " 73,
115+ " ev_intn " 72
116+ },
117+ " type " " periperal"
118+ },
119+ " I2S2ext " {
120+ " base " 0x40003400,
121+ " struct " " STM32F4xxSpi" ,
122+ " type " " periperal"
123+ },
124+ " I2S3ext " {
125+ " base " 0x40004000,
126+ " struct " " STM32F4xxSpi" ,
127+ " type " " periperal"
128+ },
129+ " IWDG " {
130+ " base " 0x40003000,
131+ " struct " " STM32F4xxIwdg" ,
132+ " type " " periperal"
133+ },
134+ " NVIC " {
135+ " base " 0xe000e100,
136+ " struct " " CortexM4Nvic" ,
137+ " type " " core peripheral"
138+ },
139+ " PERIP " {
140+ " base " 0x40000000,
141+ " size " 0x100000,
142+ " type " " mmio"
143+ },
144+ " PERIP BB " {
145+ " alias " 0x42000000,
146+ " base " 0x40000000,
147+ " size " 0x100000,
148+ " type " " bitband"
149+ },
150+ " PPB " {
151+ " base " 0xe0000000,
152+ " size " 0x10000,
153+ " type " " mmio"
154+ },
155+ " PWR " {
156+ " base " 0x40007000,
157+ " struct " " STM32F4xxPwr" ,
158+ " type " " periperal"
159+ },
160+ " RCC " {
161+ " base " 0x40023800,
162+ " struct " " STM32F4xxRcc" ,
163+ " kwargs " {
164+ " intn " 5
165+ },
166+ " type " " periperal"
167+ },
168+ " RTC " {
169+ " base " 0x40002800,
170+ " struct " " STM32F4xxRtc" ,
171+ " kwargs " {
172+ " alarm_intn " 41,
173+ " wkup_intn " 3
174+ },
175+ " type " " periperal"
176+ },
177+ " SCB " {
178+ " base " 0xe000ed00,
179+ " struct " " CortexM4Scb" ,
180+ " type " " core peripheral"
181+ },
182+ " SDIO " {
183+ " base " 0x40012c00,
184+ " struct " " STM32F4xxSdio" ,
185+ " kwargs " {
186+ " intn " 49
187+ },
188+ " type " " periperal"
189+ },
190+ " SPI1 " {
191+ " base " 0x40013000,
192+ " struct " " STM32F4xxSpi" ,
193+ " kwargs " {
194+ " intn " 35
195+ },
196+ " type " " periperal"
197+ },
198+ " SPI2 " {
199+ " base " 0x40003800,
200+ " struct " " STM32F4xxSpi" ,
201+ " kwargs " {
202+ " intn " 36
203+ },
204+ " type " " periperal"
205+ },
206+ " SPI3 " {
207+ " base " 0x40003c00,
208+ " struct " " STM32F4xxSpi" ,
209+ " kwargs " {
210+ " intn " 51
211+ },
212+ " type " " periperal"
213+ },
214+ " SPI4 " {
215+ " base " 0x40013400,
216+ " struct " " STM32F4xxSpi" ,
217+ " kwargs " {
218+ " intn " 84
219+ },
220+ " type " " periperal"
221+ },
222+ " SPI5 " {
223+ " base " 0x40015000,
224+ " struct " " STM32F4xxSpi" ,
225+ " kwargs " {
226+ " intn " 85
227+ },
228+ " type " " periperal"
229+ },
230+ " SRAM " {
231+ " base " 0x20000000,
232+ " size " 0x20000,
233+ " type " " memory"
234+ },
235+ " SRAM BB " {
236+ " alias " 0x22000000,
237+ " base " 0x20000000,
238+ " size " 0x100000,
239+ " type " " bitband"
240+ },
241+ " SYSCFG " {
242+ " base " 0x40013800,
243+ " struct " " STM32F4xxSyscfg" ,
244+ " type " " periperal"
245+ },
246+ " SYSTEM " {
247+ " base " 0x1fff0000,
248+ " size " 0x7800,
249+ " type " " memory"
250+ },
251+ " SYSTICK " {
252+ " base " 0xe000e010,
253+ " struct " " CortexM4SysTick" ,
254+ " type " " core peripheral"
255+ },
256+ " TIM1 " {
257+ " base " 0x40010000,
258+ " struct " " STM32F4xxTim" ,
259+ " kwargs " {
260+ " brk_tim9_intn " 24,
261+ " cc_intn " 27,
262+ " trg_com_tim11_intn " 26,
263+ " up_tim10_intn " 25
264+ },
265+ " type " " periperal"
266+ },
267+ " TIM10 " {
268+ " base " 0x40014400,
269+ " struct " " STM32F4xxTim" ,
270+ " type " " periperal"
271+ },
272+ " TIM11 " {
273+ " base " 0x40014800,
274+ " struct " " STM32F4xxTim" ,
275+ " type " " periperal"
276+ },
277+ " TIM2 " {
278+ " base " 0x40000000,
279+ " struct " " STM32F4xxTim" ,
280+ " kwargs " {
281+ " intn " 28
282+ },
283+ " type " " periperal"
284+ },
285+ " TIM3 " {
286+ " base " 0x40000400,
287+ " struct " " STM32F4xxTim" ,
288+ " kwargs " {
289+ " intn " 29
290+ },
291+ " type " " periperal"
292+ },
293+ " TIM4 " {
294+ " base " 0x40000800,
295+ " struct " " STM32F4xxTim" ,
296+ " kwargs " {
297+ " intn " 30
298+ },
299+ " type " " periperal"
300+ },
301+ " TIM5 " {
302+ " base " 0x40000c00,
303+ " struct " " STM32F4xxTim" ,
304+ " kwargs " {
305+ " intn " 50
306+ },
307+ " type " " periperal"
308+ },
309+ " TIM9 " {
310+ " base " 0x40014000,
311+ " struct " " STM32F4xxTim" ,
312+ " type " " periperal"
313+ },
314+ " USART1 " {
315+ " base " 0x40011000,
316+ " struct " " STM32F4xxUsart" ,
317+ " kwargs " {
318+ " intn " 37
319+ },
320+ " type " " periperal"
321+ },
322+ " USART2 " {
323+ " base " 0x40004400,
324+ " struct " " STM32F4xxUsart" ,
325+ " kwargs " {
326+ " intn " 38
327+ },
328+ " type " " periperal"
329+ },
330+ " USART6 " {
331+ " base " 0x40011400,
332+ " struct " " STM32F4xxUsart" ,
333+ " kwargs " {
334+ " intn " 71
335+ },
336+ " type " " periperal"
337+ },
338+ " WWDG " {
339+ " base " 0x40002c00,
340+ " struct " " STM32F4xxWwdg" ,
341+ " kwargs " {
342+ " intn " 0
343+ },
344+ " type " " periperal"
345+ }
346+ }
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