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rb3gen2: lpass (#800)
Enable audio support on RB3Gen2. Tested: **- output:** `aplay` to main board speaker outputs **- input** microphone not tested ``` amixer -c 0 cset iface=MIXER,name='SpkrLeft PA Volume' '20' amixer -c 0 cset iface=MIXER,name='WSA RX0 MUX' 'AIF1_PB' amixer -c 0 cset iface=MIXER,name='WSA_RX0 INP0' 'RX0' amixer -c 0 cset iface=MIXER,name='WSA_COMP1 Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrLeft WSA MODE' '0' amixer -c 0 cset iface=MIXER,name='SpkrLeft COMP Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrLeft BOOST Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrLeft DAC Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrLeft VISENSE Switch' '0' amixer -c 0 cset iface=MIXER,name='WSA_RX0 Digital Volume' '85' amixer -c 0 cset iface=MIXER,name='SpkrRight WSA MODE' '0' amixer -c 0 cset iface=MIXER,name='SpkrRight PA Volume' '20' amixer -c 0 cset iface=MIXER,name='WSA RX1 MUX' 'AIF1_PB' amixer -c 0 cset iface=MIXER,name='WSA_RX1 INP0' 'RX1' amixer -c 0 cset iface=MIXER,name='WSA_COMP2 Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrRight WSA MODE' '0' amixer -c 0 cset iface=MIXER,name='SpkrRight COMP Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrRight BOOST Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrRight DAC Switch' '1' amixer -c 0 cset iface=MIXER,name='SpkrRight VISENSE Switch' '0' amixer -c 0 cset iface=MIXER,name='WSA_RX1 Digital Volume' '85' amixer -c 0 cset iface=MIXER,name='WSA_CODEC_DMA_RX_0 Audio Mixer MULTIMEDIA0' 1 $ aplay -D plughw:0,0 test.wav $ file test.wav RIFF (little-endian) data, WAVE audio, Microsoft PCM, 16 bit, stereo 48000 Hz ````
2 parents eed01e0 + 16cf3fe commit 6e182b5

11 files changed

+673
-0
lines changed

recipes-kernel/linux/linux-yocto-dev.bbappend

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@@ -13,6 +13,15 @@ SRC_URI:append:qcom = " \
1313
file://qcm6490-board-dts/0002-arm64-dts-qcom-qcs6490-rb3gen2-vision-mezzanine-Add-.patch \
1414
file://qcm6490-board-dts/0002-media-dt-bindings-update-clocks-for-sc7280-camss.patch \
1515
file://qcm6490-board-dts/0001-PENDING-enable-xHCI.patch \
16+
file://qcm6490-board-dts/0001-dt-bindings-clock-qcom-Add-compatible-for.patch \
17+
file://qcm6490-board-dts/0002-arm64-dts-qcom-qcm6490-idp-Update-the-LPASS.patch \
18+
file://qcm6490-board-dts/0003-arm64-dts-qcom-qcs6490-rb3gen2-Update-the-LPASS-audi.patch \
19+
file://qcm6490-board-dts/0001-arm64-dts-qcom-sc7280-Add-gpr-node.patch \
20+
file://qcm6490-board-dts/0002-arm64-dts-qcom-sc7280-Add-WSA-SoundWire-and-LPASS-su.patch \
21+
file://qcm6490-board-dts/0003-arm64-dts-qcom-qcs6490-rb3gen2-Modify-WSA-and-VA-mac.patch \
22+
file://qcm6490-board-dts/0004-arm64-dts-qcom-qcs6490-rb3gen2-add-WSA8830-speakers-.patch \
23+
file://qcm6490-board-dts/0005-arm64-dts-qcom-qcs6490-rb3gen2-Add-sound-card.patch \
24+
file://qcm6490-board-dts/0001-dts-rb3gen2-soundwire-checkin.patch \
1625
file://workarounds/0001-QCLINUX-arm64-dts-qcom-qcm6490-disable-sdhc1-for-ufs.patch \
1726
file://workarounds/0001-PENDING-arm64-dts-qcom-Remove-voltage-vote-support-f.patch \
1827
file://drivers/0003-PCI-Add-new-start_link-stop_link-function-ops.patch \
@@ -22,6 +31,7 @@ SRC_URI:append:qcom = " \
2231
file://drivers/0007-PCI-PCI-Add-pcie_is_link_active-to-determine-if-the-.patch \
2332
file://drivers/0008-PCI-pwrctrl-Add-power-control-driver-for-tc956x.patch \
2433
file://drivers/0001-media-qcom-camss-update-clock-names-for-sc7280.patch \
34+
file://drivers/0004-clk-qcom-lpassaudiocc-sc7280-Add-support-for-LPASS-r.patch \
2535
"
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2737
# Include additional kernel configs.
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@@ -0,0 +1,89 @@
1+
From a475928e65aa6808a9fdd56b8612f355b3c16c67 Mon Sep 17 00:00:00 2001
2+
From: Taniya Das <[email protected]>
3+
Date: Sat, 22 Feb 2025 09:17:15 +0100
4+
Subject: [PATCH 4/4] clk: qcom: lpassaudiocc-sc7280: Add support for LPASS
5+
resets for QCM6490
6+
7+
On the QCM6490 boards, the LPASS firmware controls the complete clock
8+
controller functionalities and associated power domains. However, only
9+
the LPASS resets required to be controlled by the high level OS. Thus,
10+
add support for the resets in the clock driver to enable the Audio SW
11+
driver to assert/deassert the audio resets as needed.
12+
13+
Reviewed-by: Dmitry Baryshkov <[email protected]>
14+
Signed-off-by: Taniya Das <[email protected]>
15+
Upstream-Status: Submitted [https://lore.kernel.org/linux-arm-msm/[email protected]/]
16+
---
17+
drivers/clk/qcom/lpassaudiocc-sc7280.c | 23 +++++++++++++++++++----
18+
1 file changed, 19 insertions(+), 4 deletions(-)
19+
20+
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
21+
index 45e726477086..22169da08a51 100644
22+
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
23+
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
24+
@@ -1,6 +1,7 @@
25+
// SPDX-License-Identifier: GPL-2.0-only
26+
/*
27+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
30+
31+
#include <linux/clk-provider.h>
32+
@@ -713,14 +714,24 @@ static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
33+
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
34+
};
35+
36+
+static const struct regmap_config lpass_audio_cc_sc7280_reset_regmap_config = {
37+
+ .name = "lpassaudio_cc_reset",
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+ .reg_bits = 32,
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+ .reg_stride = 4,
40+
+ .val_bits = 32,
41+
+ .fast_io = true,
42+
+ .max_register = 0xc8,
43+
+};
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+
45+
static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
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- .config = &lpass_audio_cc_sc7280_regmap_config,
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+ .config = &lpass_audio_cc_sc7280_reset_regmap_config,
48+
.resets = lpass_audio_cc_sc7280_resets,
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.num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
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};
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52+
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
53+
- { .compatible = "qcom,sc7280-lpassaudiocc" },
54+
+ { .compatible = "qcom,qcm6490-lpassaudiocc", .data = &lpass_audio_cc_reset_sc7280_desc },
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+ { .compatible = "qcom,sc7280-lpassaudiocc", .data = &lpass_audio_cc_sc7280_desc },
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{ }
57+
};
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MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table);
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@@ -752,13 +763,17 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
60+
struct regmap *regmap;
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int ret;
62+
63+
+ desc = device_get_match_data(&pdev->dev);
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+
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+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcm6490-lpassaudiocc"))
66+
+ return qcom_cc_probe_by_index(pdev, 1, desc);
67+
+
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ret = lpass_audio_setup_runtime_pm(pdev);
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if (ret)
70+
return ret;
71+
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lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc";
73+
lpass_audio_cc_sc7280_regmap_config.max_register = 0x2f000;
74+
- desc = &lpass_audio_cc_sc7280_desc;
75+
76+
regmap = qcom_cc_map(pdev, desc);
77+
if (IS_ERR(regmap)) {
78+
@@ -772,7 +787,7 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
79+
regmap_write(regmap, 0x4, 0x3b);
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regmap_write(regmap, 0x8, 0xff05);
81+
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- ret = qcom_cc_really_probe(&pdev->dev, &lpass_audio_cc_sc7280_desc, regmap);
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+ ret = qcom_cc_really_probe(&pdev->dev, desc, regmap);
84+
if (ret) {
85+
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
86+
goto exit;
87+
--
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2.34.1
89+
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@@ -0,0 +1,75 @@
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From d917cb1baa4c2144317c3d38a3977c7e6dea9cf7 Mon Sep 17 00:00:00 2001
2+
From: Mohammad Rafi Shaik <[email protected]>
3+
Date: Mon, 17 Mar 2025 11:11:44 +0530
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Subject: [PATCH 1/5] arm64: dts: qcom: sc7280: Add gpr node
5+
6+
Add GPR node along with APM(Audio Process Manager) and PRM(Proxy
7+
resource Manager) audio services.
8+
9+
Signed-off-by: Mohammad Rafi Shaik <[email protected]>
10+
Co-developed-by: Prasad Kumpatla <[email protected]>
11+
Signed-off-by: Prasad Kumpatla <[email protected]>
12+
13+
Upstream-Status: Submitted [https://lore.kernel.org/linux-arm-msm/[email protected]/]
14+
---
15+
arch/arm64/boot/dts/qcom/sc7280.dtsi | 37 ++++++++++++++++++++++++++++
16+
1 file changed, 37 insertions(+)
17+
18+
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
19+
index 7c4f48783656..4ec39782f772 100644
20+
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
21+
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
22+
@@ -25,6 +25,8 @@
23+
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
24+
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
25+
#include <dt-bindings/soc/qcom,apr.h>
26+
+#include <dt-bindings/soc/qcom,gpr.h>
27+
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
28+
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
29+
#include <dt-bindings/sound/qcom,lpass.h>
30+
#include <dt-bindings/thermal/thermal.h>
31+
@@ -3865,6 +3867,41 @@ q6routing: routing {
32+
};
33+
};
34+
35+
+ gpr {
36+
+ compatible = "qcom,gpr";
37+
+ qcom,glink-channels = "adsp_apps";
38+
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
39+
+ qcom,intents = <512 20>;
40+
+ #address-cells = <1>;
41+
+ #size-cells = <0>;
42+
+
43+
+ q6apm: service@1 {
44+
+ compatible = "qcom,q6apm";
45+
+ reg = <GPR_APM_MODULE_IID>;
46+
+ #sound-dai-cells = <0>;
47+
+
48+
+ q6apmdai: dais {
49+
+ compatible = "qcom,q6apm-dais";
50+
+ iommus = <&apps_smmu 0x1801 0x0>;
51+
+ };
52+
+
53+
+ q6apmbedai: bedais {
54+
+ compatible = "qcom,q6apm-lpass-dais";
55+
+ #sound-dai-cells = <1>;
56+
+ };
57+
+ };
58+
+
59+
+ q6prm: service@2 {
60+
+ compatible = "qcom,q6prm";
61+
+ reg = <GPR_PRM_MODULE_IID>;
62+
+
63+
+ q6prmcc: clock-controller {
64+
+ compatible = "qcom,q6prm-lpass-clocks";
65+
+ #clock-cells = <2>;
66+
+ };
67+
+ };
68+
+ };
69+
+
70+
fastrpc {
71+
compatible = "qcom,fastrpc";
72+
qcom,glink-channels = "fastrpcglink-apps-dsp";
73+
--
74+
2.34.1
75+
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@@ -0,0 +1,43 @@
1+
From d6e1925bc276590b40943d233cf198a64fb9bd19 Mon Sep 17 00:00:00 2001
2+
From: Taniya Das <[email protected]>
3+
Date: Wed, 5 Mar 2025 16:19:25 +0100
4+
Subject: [PATCH 1/4] dt-bindings: clock: qcom: Add compatible for
5+
6+
On the QCM6490 boards, the LPASS firmware controls the complete clock
7+
controller functionalities and associated power domains. However, only
8+
the LPASS resets required to be controlled by the high level OS. Thus,
9+
add the new QCM6490 compatible to support the reset functionality for
10+
Low Power Audio subsystem.
11+
12+
Signed-off-by: Taniya Das <[email protected]>
13+
Upstream-Status: Submitted [https://lore.kernel.org/linux-arm-msm/[email protected]/]
14+
---
15+
.../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 5 ++++-
16+
1 file changed, 4 insertions(+), 1 deletion(-)
17+
18+
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
19+
index 488d63959424..99ab9106009f 100644
20+
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
21+
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
22+
@@ -20,6 +20,7 @@ description: |
23+
properties:
24+
compatible:
25+
enum:
26+
+ - qcom,qcm6490-lpassaudiocc
27+
- qcom,sc7280-lpassaoncc
28+
- qcom,sc7280-lpassaudiocc
29+
- qcom,sc7280-lpasscorecc
30+
@@ -68,7 +69,9 @@ allOf:
31+
properties:
32+
compatible:
33+
contains:
34+
- const: qcom,sc7280-lpassaudiocc
35+
+ enum:
36+
+ - qcom,qcm6490-lpassaudiocc
37+
+ - qcom,sc7280-lpassaudiocc
38+
39+
then:
40+
properties:
41+
--
42+
2.34.1
43+
Lines changed: 40 additions & 0 deletions
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@@ -0,0 +1,40 @@
1+
From d8535dbed058a3cb8c43a343624b315501b16433 Mon Sep 17 00:00:00 2001
2+
From: Jorge Ramirez-Ortiz <[email protected]>
3+
Date: Wed, 26 Mar 2025 17:49:03 +0100
4+
Subject: [PATCH] dts: rb3gen2: fix soundwire probe
5+
6+
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
7+
Upstream-Status: Pending [shared internally]
8+
---
9+
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 8 ++++++--
10+
1 file changed, 6 insertions(+), 2 deletions(-)
11+
12+
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
13+
index b993665ca953..041bb96ca69a 100644
14+
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
15+
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
16+
@@ -1116,8 +1116,8 @@ tc956x_rst_state: tc956x-rst-state {
17+
};
18+
19+
&swr2 {
20+
- qcom,din-ports = <0>;
21+
- qcom,dout-ports = <8>;
22+
+ qcom,din-ports = <2>;
23+
+ qcom,dout-ports = <6>;
24+
25+
left_spkr: speaker@0,1 {
26+
compatible = "sdw10217020200";
27+
@@ -1142,6 +1142,10 @@ right_spkr: speaker@0,2 {
28+
};
29+
};
30+
31+
+&swr2 {
32+
+ status = "okay";
33+
+};
34+
+
35+
&tlmm {
36+
gpio-reserved-ranges = <32 2>, /* ADSP */
37+
<48 4>; /* NFC */
38+
--
39+
2.34.1
40+
Lines changed: 33 additions & 0 deletions
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@@ -0,0 +1,33 @@
1+
From 1946a1cd6f785c856016a08ec23b76ba485ea6e6 Mon Sep 17 00:00:00 2001
2+
From: Taniya Das <[email protected]>
3+
Date: Sat, 22 Feb 2025 09:18:51 +0100
4+
Subject: [PATCH 2/4] arm64: dts: qcom: qcm6490-idp: Update the LPASS
5+
6+
Update the lpassaudio node to support the new compatible as the
7+
lpassaudio needs to support the reset functionality on the
8+
QCM6490 IDP board and the rest of the Audio functionality would be
9+
provided from the LPASS firmware.
10+
11+
Reviewed-by: Dmitry Baryshkov <[email protected]>
12+
Signed-off-by: Taniya Das <[email protected]>
13+
Upstream-Status: Submitted [https://lore.kernel.org/linux-arm-msm/[email protected]/]
14+
---
15+
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 5 +++++
16+
1 file changed, 5 insertions(+)
17+
18+
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
19+
index 391f1e9efc8b..8b7d67874fce 100644
20+
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
21+
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
22+
@@ -799,3 +799,8 @@ &wifi {
23+
24+
status = "okay";
25+
};
26+
+
27+
+&lpass_audiocc {
28+
+ compatible = "qcom,qcm6490-lpassaudiocc";
29+
+ /delete-property/ power-domains;
30+
+};
31+
--
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2.34.1
33+

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