plat-qcom: kodiak: enable QFPROM driver

Enable QFPROM driver for Kodiak platform and register the
Security Control and Clock Control memory regions required
for secure OTP fuse operations.

Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com>

Author: zelvam95

core/arch/arm/plat-qcom/conf.mk

@@ -28,6 +28,8 @@ $(call force,CFG_CMD_DB,y)
 
 $(call force,CFG_RPMH_CLIENT,y)
 
+$(call force,CFG_QFPROM,y)
+
 CFG_TZDRAM_START ?= 0x1c300000
 CFG_TEE_RAM_VA_SIZE ?= 0x200000
 CFG_TA_RAM_VA_SIZE ?= 0x1c00000

core/arch/arm/plat-qcom/main.c

@@ -30,6 +30,18 @@ register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AOP_SS_MSG_RAM_START_ADDRESS_BASE,
 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RPMH_BASE_ADDR, RPMH_RSC_SIZE);
 #endif
 
+#ifdef TCSR_MUTEX_BASE
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, TCSR_MUTEX_BASE, TCSR_MUTEX_SIZE);
+#endif
+
+#ifdef SECURITY_CONTROL_BASE
+register_phys_mem(MEM_AREA_IO_SEC, SECURITY_CONTROL_BASE,
+		  SECURITY_CONTROL_SIZE);
+#endif
+#ifdef CLK_CTL_BASE
+register_phys_mem(MEM_AREA_IO_SEC, CLK_CTL_BASE, CLK_CTL_SIZE);
+#endif
+
 register_ddr(DRAM0_BASE, DRAM0_SIZE);
 #ifdef DRAM1_BASE
 register_ddr(DRAM1_BASE, DRAM1_SIZE);

core/arch/arm/plat-qcom/platform_config.h

@@ -37,6 +37,17 @@
 /* RPMH RSC base address */
 #define RPMH_BASE_ADDR			UL(0x18200000)
 #define RPMH_RSC_SIZE			UL(0x40000)
+
+/* QFPROM and Security Control */
+#define SECURITY_CONTROL_BASE		UL(0x00780000)
+#define SECURITY_CONTROL_SIZE		UL(0x10000)
+#define CLK_CTL_BASE			UL(0x00100000)
+#define CLK_CTL_SIZE			UL(0x1F0000)
+
+/* TCSR Hardware Mutex */
+#define TCSR_MUTEX_BASE			UL(0x01F40000)
+#define TCSR_MUTEX_SIZE			UL(0x40000)
+
 #endif
 
 #endif /*PLATFORM_CONFIG_H*/