@@ -491,6 +491,263 @@ diff -Nru mesa-25.2.0-orig/debian/patches/path_max.diff mesa-25.2.0/debian/patch
491491 static int (*backends[])(struct pipe_loader_device **, int) = {
492492+ #ifdef HAVE_LIBDRM
493493+ &pipe_loader_drm_probe,
494+ --- mesa-25.2.0-orig/debian/patches/35316.patch 2025-06-17 11:40:36.606796770 +0300
495+ +++ mesa-25.2.0/debian/patches/35316.patch 2025-06-17 15:02:11.471138105 +0300
496+ @@ -0,0 +1,254 @@
497+ +From: Lakshman Chandu Kondreddy <
[email protected] >
498+ +Subject: freedreno: Add sampling support for RGB/BGR 24-bit component texture formats
499+ +Origin: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35316
500+ +
501+ +From e56ef6179653e0b5574d1b9648db25c9cf6e3a6e Mon Sep 17 00:00:00 2001
502+ +From: "Petar G. Georgiev" <
[email protected] >
503+ +Date: Mon, 12 May 2025 11:49:06 +0530
504+ +Subject: [PATCH 1/4] util: Add pack and unpack for R8G8B8/B8G8R8
505+ +
506+ +This helps in packing and unpacking the R8G8B8/B8G8R8
507+ +pipe formats which are of uint8 type.
508+ +
509+ +Signed-off-by: Petar G. Georgiev <
[email protected] >
510+ +Signed-off-by: Lakshman Chandu Kondreddy <
[email protected] >
511+ +---
512+ + src/util/u_pack_color.h | 27 +++++++++++++++++++++++++++
513+ + 1 file changed, 27 insertions(+)
514+ +
515+ +diff --git a/src/util/u_pack_color.h b/src/util/u_pack_color.h
516+ +index 7d5bf7f35457f..b646729fda540 100644
517+ +--- a/src/util/u_pack_color.h
518+ ++++ b/src/util/u_pack_color.h
519+ +@@ -94,6 +94,16 @@ util_pack_color_ub(uint8_t r, uint8_t g, uint8_t b, uint8_t a,
520+ + uc->ui[0] = (b << 24) | (g << 16) | (r << 8) | 0xff;
521+ + }
522+ + return;
523+ ++ case PIPE_FORMAT_R8G8B8_UNORM:
524+ ++ {
525+ ++ uc->ui[0] = (b << 16) | (g << 8) | r;
526+ ++ }
527+ ++ return;
528+ ++ case PIPE_FORMAT_B8G8R8_UNORM:
529+ ++ {
530+ ++ uc->ui[0] = (r << 16) | (g << 8) | b;
531+ ++ }
532+ ++ return;
533+ + case PIPE_FORMAT_B5G6R5_UNORM:
534+ + {
535+ + uc->us = ((r & 0xf8) << 8) | ((g & 0xfc) << 3) | (b >> 3);
536+ +@@ -219,6 +229,23 @@ util_unpack_color_ub(enum pipe_format format, union util_color *uc,
537+ + *a = (uint8_t) 0xff;
538+ + }
539+ + return;
540+ ++ case PIPE_FORMAT_R8G8B8_UNORM:
541+ ++ {
542+ ++ uint32_t p = uc->ui[0];
543+ ++ *r = (uint8_t) (p & 0xff);
544+ ++ *g = (uint8_t) ((p >> 8) & 0xff);
545+ ++ *b = (uint8_t) ((p >> 16) & 0xff);
546+ ++ *a = (uint8_t) 0xff;
547+ ++ }
548+ ++ return;
549+ ++ case PIPE_FORMAT_B8G8R8_UNORM:
550+ ++ {
551+ ++ uint32_t p = uc->ui[0];
552+ ++ *r = (uint8_t) ((p >> 16) & 0xff);
553+ ++ *g = (uint8_t) ((p >> 8) & 0xff);
554+ ++ *b = (uint8_t) (p & 0xff);
555+ ++ *a = (uint8_t) 0xff;
556+ ++ }
557+ + case PIPE_FORMAT_B5G6R5_UNORM:
558+ + {
559+ + uint16_t p = uc->us;
560+ +--
561+ +GitLab
562+ +
563+ +
564+ +From cd56b02b49047b27a4942e8c0ab8302b94101d67 Mon Sep 17 00:00:00 2001
565+ +From: Rob Clark <
[email protected] >
566+ +Date: Wed, 25 Jun 2025 10:39:24 -0700
567+ +Subject: [PATCH 2/4] freedreno/layout: Support for NPoT formats
568+ +
569+ +Three component formats don't get UBWC, but do get their pitch aligned
570+ +to the next PoT size.
571+ +
572+ +Signed-off-by: Rob Clark <
[email protected] >
573+ +---
574+ + src/freedreno/fdl/fd6_layout.c | 55 +++++++++++++++++++++-------------
575+ + 1 file changed, 35 insertions(+), 20 deletions(-)
576+ +
577+ +diff --git a/src/freedreno/fdl/fd6_layout.c b/src/freedreno/fdl/fd6_layout.c
578+ +index f4d6adfcb4625..d4cd785f63afe 100644
579+ +--- a/src/freedreno/fdl/fd6_layout.c
580+ ++++ b/src/freedreno/fdl/fd6_layout.c
581+ +@@ -139,16 +139,22 @@ fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
582+ + layout->layer_first = !is_3d;
583+ + layout->is_mutable = is_mutable;
584+ +
585+ +- fdl6_get_ubwc_blockwidth(layout, &ubwc_blockwidth, &ubwc_blockheight);
586+ +-
587+ +- /* For simplicity support UBWC only for 3D images without mipmaps,
588+ +- * most d3d11 games don't use mipmaps for 3D images.
589+ +- */
590+ +- if (depth0 > 1 && mip_levels > 1)
591+ ++ if (!util_is_power_of_two_or_zero(layout->cpp)) {
592+ ++ /* R8G8B8 and other 3 component formats don't get UBWC: */
593+ ++ ubwc_blockwidth = ubwc_blockheight = 0;
594+ + layout->ubwc = false;
595+ ++ } else {
596+ ++ fdl6_get_ubwc_blockwidth(layout, &ubwc_blockwidth, &ubwc_blockheight);
597+ +
598+ +- if (ubwc_blockwidth == 0)
599+ +- layout->ubwc = false;
600+ ++ /* For simplicity support UBWC only for 3D images without mipmaps,
601+ ++ * most d3d11 games don't use mipmaps for 3D images.
602+ ++ */
603+ ++ if (depth0 > 1 && mip_levels > 1)
604+ ++ layout->ubwc = false;
605+ ++
606+ ++ if (ubwc_blockwidth == 0)
607+ ++ layout->ubwc = false;
608+ ++ }
609+ +
610+ + assert(!force_ubwc || layout->ubwc);
611+ +
612+ +@@ -180,19 +186,28 @@ fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
613+ + } else {
614+ + layout->base_align = 64;
615+ + layout->pitchalign = 0;
616+ +- /* align pitch to at least 16 pixels:
617+ +- * both turnip and galium assume there is enough alignment for 16x4
618+ +- * aligned gmem store. turnip can use CP_BLIT to work without this
619+ +- * extra alignment, but gallium driver doesn't implement it yet
620+ +- */
621+ +- if (layout->cpp > 4)
622+ +- layout->pitchalign = fdl_cpp_shift(layout) - 2;
623+ +
624+ +- /* when possible, use a bit more alignment than necessary
625+ +- * presumably this is better for performance?
626+ +- */
627+ +- if (!explicit_layout)
628+ +- layout->pitchalign = fdl_cpp_shift(layout);
629+ ++ if (util_is_power_of_two_or_zero(layout->cpp)) {
630+ ++ /* align pitch to at least 16 pixels:
631+ ++ * both turnip and galium assume there is enough alignment for 16x4
632+ ++ * aligned gmem store. turnip can use CP_BLIT to work without this
633+ ++ * extra alignment, but gallium driver doesn't implement it yet
634+ ++ */
635+ ++ if (layout->cpp > 4)
636+ ++ layout->pitchalign = fdl_cpp_shift(layout) - 2;
637+ ++
638+ ++ /* when possible, use a bit more alignment than necessary
639+ ++ * presumably this is better for performance?
640+ ++ */
641+ ++ if (!explicit_layout)
642+ ++ layout->pitchalign = fdl_cpp_shift(layout);
643+ ++ } else {
644+ ++ /* 3 component formats have pitch aligned as their counterpart
645+ ++ * 4 component formats
646+ ++ */
647+ ++ layout->cpp_shift = ffs(util_next_power_of_two(layout->cpp)) - 1;
648+ ++ layout->pitchalign = layout->cpp_shift;
649+ ++ }
650+ +
651+ + /* not used, avoid "may be used uninitialized" warning */
652+ + heightalign = 1;
653+ +--
654+ +GitLab
655+ +
656+ +
657+ +From 2837d27c4dce134231fc583a8c0d45e0ba22fe23 Mon Sep 17 00:00:00 2001
658+ +From: "Petar G. Georgiev" <
[email protected] >
659+ +Date: Sat, 10 May 2025 01:04:49 +0530
660+ +Subject: [PATCH 3/4] freedreno/fdl: Add support for RGB888/BGR888 pipe formats
661+ + in render buffer creation
662+ +
663+ +This enables the rendering of RGB/BGR 24-bit format buffers directly
664+ +onto the framebuffer. For RGB888, support already exists for vertex and
665+ +texture formats, so render buffer format support has been added. For
666+ +BGR888, support for vertex, texture, and render buffer formats has been
667+ +added. The internal format chosen for both RGB888 and BGR888 is GL_RGB8.
668+ +
669+ +Change-Id: I0557389dba05d3b44d7b935f02683df17e41fbd2
670+ +Signed-off-by: Petar G. Georgiev <
[email protected] >
671+ +Signed-off-by: Lakshman Chandu Kondreddy <
[email protected] >
672+ +---
673+ + src/freedreno/fdl/fd6_format_table.c | 12 ++++++++----
674+ + 1 file changed, 8 insertions(+), 4 deletions(-)
675+ +
676+ +diff --git a/src/freedreno/fdl/fd6_format_table.c b/src/freedreno/fdl/fd6_format_table.c
677+ +index 55d42538debd5..994c15c120e61 100644
678+ +--- a/src/freedreno/fdl/fd6_format_table.c
679+ ++++ b/src/freedreno/fdl/fd6_format_table.c
680+ +@@ -121,12 +121,16 @@ static const struct fd6_format formats[PIPE_FORMAT_COUNT] = {
681+ + _TC(A4B4G4R4_UNORM, 4_4_4_4_UNORM, XYZW),
682+ +
683+ + /* 24-bit */
684+ +- VT_(R8G8B8_UNORM, 8_8_8_UNORM, WZYX),
685+ +- VT_(R8G8B8_SNORM, 8_8_8_SNORM, WZYX),
686+ +- VT_(R8G8B8_UINT, 8_8_8_UINT, WZYX),
687+ +- VT_(R8G8B8_SINT, 8_8_8_SINT, WZYX),
688+ ++ VTC(R8G8B8_UNORM, 8_8_8_UNORM, WZYX),
689+ ++ VTC(R8G8B8_SNORM, 8_8_8_SNORM, WZYX),
690+ ++ VTC(R8G8B8_UINT, 8_8_8_UINT, WZYX),
691+ ++ VTC(R8G8B8_SINT, 8_8_8_SINT, WZYX),
692+ + V__(R8G8B8_USCALED, 8_8_8_UINT, WZYX),
693+ + V__(R8G8B8_SSCALED, 8_8_8_SINT, WZYX),
694+ ++ VTC(B8G8R8_UNORM, 8_8_8_UNORM, WXYZ),
695+ ++ VTC(B8G8R8_SNORM, 8_8_8_SNORM, WXYZ),
696+ ++ VTC(B8G8R8_UINT, 8_8_8_UINT, WXYZ),
697+ ++ VTC(B8G8R8_SINT, 8_8_8_SINT, WXYZ),
698+ +
699+ + /* 32-bit */
700+ + V__(R32_UNORM, 32_UNORM, WZYX),
701+ +--
702+ +GitLab
703+ +
704+ +
705+ +From 31b49cf057c27f41a123e615092f00762caaf329 Mon Sep 17 00:00:00 2001
706+ +From: "Petar G. Georgiev" <
[email protected] >
707+ +Date: Sat, 10 May 2025 01:11:24 +0530
708+ +Subject: [PATCH 4/4] freedreno/a6xx: Add support for some NPOT block size
709+ + formats
710+ +
711+ +This enables support for sampler view and shader image for
712+ +non power of two formats such as RGB888/BGR888.
713+ +As the above mentioned formats are of 24 bit, block size
714+ +for each format is 3. So added condition to check this.
715+ +
716+ +Change-Id: Ie48dfd4604ad9392fc655fd7a3b49c8c6a7a7229
717+ +Co-Developed-by: Lakshman Chandu Kondreddy <
[email protected] >
718+ +Signed-off-by: Petar G. Georgiev <
[email protected] >
719+ +Signed-off-by: Lakshman Chandu Kondreddy <
[email protected] >
720+ +---
721+ + src/gallium/drivers/freedreno/a6xx/fd6_screen.cc | 13 ++++++++-----
722+ + 1 file changed, 8 insertions(+), 5 deletions(-)
723+ +
724+ +diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_screen.cc b/src/gallium/drivers/freedreno/a6xx/fd6_screen.cc
725+ +index 0b593cef4f4df..3f7387b6c345d 100644
726+ +--- a/src/gallium/drivers/freedreno/a6xx/fd6_screen.cc
727+ ++++ b/src/gallium/drivers/freedreno/a6xx/fd6_screen.cc
728+ +@@ -67,11 +67,14 @@ fd6_screen_is_format_supported(struct pipe_screen *pscreen,
729+ + bool has_color = fd6_color_format(format, TILE6_LINEAR) != FMT6_NONE;
730+ + bool has_tex = fd6_texture_format_supported(screen->info, format, TILE6_LINEAR, false);
731+ +
732+ +- if ((usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) &&
733+ +- has_tex &&
734+ +- (target == PIPE_BUFFER ||
735+ +- util_is_power_of_two_or_zero(util_format_get_blocksize(format)))) {
736+ +- retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
737+ ++ if ((usage & PIPE_BIND_SHADER_IMAGE) && has_tex &&
738+ ++ (target == PIPE_BUFFER || (util_format_get_blocksize(format) == 3)
739+ ++ || util_is_power_of_two_or_zero(util_format_get_blocksize(format)))) {
740+ ++ retval |= usage & PIPE_BIND_SHADER_IMAGE;
741+ ++ }
742+ ++
743+ ++ if ((usage & PIPE_BIND_SAMPLER_VIEW) && has_tex) {
744+ ++ retval |= usage & PIPE_BIND_SAMPLER_VIEW;
745+ + }
746+ +
747+ + if (usage & PIPE_BIND_SHADER_IMAGE) {
748+ +--
749+ +GitLab
750+ +
494751diff -Nru mesa-25.2.0-orig/debian/patches/series mesa-25.2.0/debian/patches/series
495752--- mesa-25.2.0-orig/debian/patches/series 2025-06-17 14:44:27.640967846 +0300
496753+++ mesa-25.2.0/debian/patches/series 2025-06-17 14:45:04.690440415 +0300
@@ -499,3 +756,4 @@ diff -Nru mesa-25.2.0-orig/debian/patches/series mesa-25.2.0/debian/patches/seri
499756 disable_ppc64el_assembly.diff
500757 drisw-Avoid-crashing-when-swrast_loader-NULL.patch
501758-etnaviv-add-support-for-texelfetch.patch
759+ +35316.patch
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