1515import pytest
1616
1717import cirq
18+ import cirq .google as cg
1819
1920
2021@pytest .mark .parametrize ('gate_type,qubit_count' , (
21- (cirq .SYC , 2 ),
22+ (cg .SYC , 2 ),
2223 (cirq .PhasedXPowGate (phase_exponent = 0.1 ), 1 ),
2324 (cirq .PhasedXPowGate (exponent = 0.5 , phase_exponent = 0.1 ), 1 ),
2425))
@@ -32,13 +33,13 @@ def test_consistent_protocols(gate_type, qubit_count):
3233
3334
3435def test_syc_str_repr ():
35- assert str (cirq .SYC ) == 'SYC'
36- assert repr (cirq .SYC ) == 'cirq.SYC'
36+ assert str (cg .SYC ) == 'SYC'
37+ assert repr (cg .SYC ) == 'cirq.google .SYC'
3738
3839
3940def test_syc_circuit_diagram ():
4041 a , b = cirq .LineQubit .range (2 )
41- circuit = cirq .Circuit .from_ops (cirq .SYC (a , b ))
42+ circuit = cirq .Circuit .from_ops (cg .SYC (a , b ))
4243 cirq .testing .assert_has_diagram (circuit , """
43440: ───SYC───
4445 │
@@ -47,12 +48,12 @@ def test_syc_circuit_diagram():
4748
4849
4950def test_syc_is_specific_fsim ():
50- assert cirq .SYC == cirq .FSimGate (theta = np .pi / 2 , phi = np .pi / 6 )
51+ assert cg .SYC == cirq .FSimGate (theta = np .pi / 2 , phi = np .pi / 6 )
5152
5253
5354def test_syc_unitary ():
5455 cirq .testing .assert_allclose_up_to_global_phase (
55- cirq .unitary (cirq .SYC ),
56+ cirq .unitary (cg .SYC ),
5657 np .array ([
5758 [1 , 0 , 0 , 0 ],
5859 [0 , 0 , - 1j , 0 ],
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