Use GoogleCZTargetGateset; add device gateset as additional gates in target gatesets (#5765)

* GridDevice target gateset generation logic now matches all required gates for a particular gateset, rather than just the 2q gate.
* In target gatesets that support additional_gates, it's set to all gates in a device's gateset other than required gates in the target gateset, so that device gates are not decomposed during circuit transformation.

First commit is from #5744

@tanujkhattar 
cc @dstrain115

Author: verult

cirq-core/cirq/transformers/target_gatesets/cz_gateset.py

@@ -56,7 +56,7 @@ def __init__(
             allow_partial_czs: If set, all powers of the form `cirq.CZ**t`, and not just
              `cirq.CZ`, are part of this gateset.
             additional_gates: Sequence of additional gates / gate families which should also
-              be "accepted" by this gateset. Defaults to `cirq.GlobalPhaseGate`.
+              be "accepted" by this gateset. This is empty by default.
         """
         super().__init__(
             ops.CZPowGate if allow_partial_czs else ops.CZ,

cirq-core/cirq/transformers/target_gatesets/sqrt_iswap_gateset.py

@@ -62,7 +62,7 @@ def __init__(
             use_sqrt_iswap_inv: If True, `cirq.SQRT_ISWAP_INV` is used as part of the gateset,
                 instead of `cirq.SQRT_ISWAP`.
             additional_gates: Sequence of additional gates / gate families which should also
-              be "accepted" by this gateset. Defaults to `cirq.GlobalPhaseGate`.
+              be "accepted" by this gateset. This is empty by default.
 
         Raises:
             ValueError: If `required_sqrt_iswap_count` is specified and is not 0, 1, 2, or 3.

cirq-google/cirq_google/devices/grid_device.py

@@ -39,19 +39,39 @@
 from cirq_google.experimental import ops as experimental_ops
 
 
-SYC_GATE_FAMILY = cirq.GateFamily(ops.SYC)
-SQRT_ISWAP_GATE_FAMILY = cirq.GateFamily(cirq.SQRT_ISWAP)
-SQRT_ISWAP_INV_GATE_FAMILY = cirq.GateFamily(cirq.SQRT_ISWAP_INV)
-CZ_GATE_FAMILY = cirq.GateFamily(cirq.CZ)
-PHASED_XZ_GATE_FAMILY = cirq.GateFamily(cirq.PhasedXZGate)
-VIRTUAL_ZPOW_GATE_FAMILY = cirq.GateFamily(cirq.ZPowGate, tags_to_ignore=[ops.PhysicalZTag()])
-PHYSICAL_ZPOW_GATE_FAMILY = cirq.GateFamily(cirq.ZPowGate, tags_to_accept=[ops.PhysicalZTag()])
-COUPLER_PULSE_GATE_FAMILY = cirq.GateFamily(experimental_ops.CouplerPulse)
-MEASUREMENT_GATE_FAMILY = cirq.GateFamily(cirq.MeasurementGate)
-WAIT_GATE_FAMILY = cirq.GateFamily(cirq.WaitGate)
+# Gate family constants used in various parts of GridDevice logic.
+_SYC_GATE_FAMILY = cirq.GateFamily(ops.SYC)
+_SQRT_ISWAP_GATE_FAMILY = cirq.GateFamily(cirq.SQRT_ISWAP)
+_SQRT_ISWAP_INV_GATE_FAMILY = cirq.GateFamily(cirq.SQRT_ISWAP_INV)
+_CZ_GATE_FAMILY = cirq.GateFamily(cirq.CZ)
+_PHASED_XZ_GATE_FAMILY = cirq.GateFamily(cirq.PhasedXZGate)
+_VIRTUAL_ZPOW_GATE_FAMILY = cirq.GateFamily(cirq.ZPowGate, tags_to_ignore=[ops.PhysicalZTag()])
+_PHYSICAL_ZPOW_GATE_FAMILY = cirq.GateFamily(cirq.ZPowGate, tags_to_accept=[ops.PhysicalZTag()])
+_COUPLER_PULSE_GATE_FAMILY = cirq.GateFamily(experimental_ops.CouplerPulse)
+_MEASUREMENT_GATE_FAMILY = cirq.GateFamily(cirq.MeasurementGate)
+_WAIT_GATE_FAMILY = cirq.GateFamily(cirq.WaitGate)
+
+_SYC_FSIM_GATE_FAMILY = ops.FSimGateFamily(gates_to_accept=[ops.SYC])
+_SQRT_ISWAP_FSIM_GATE_FAMILY = ops.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP])
+_SQRT_ISWAP_INV_FSIM_GATE_FAMILY = ops.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV])
+_CZ_FSIM_GATE_FAMILY = ops.FSimGateFamily(gates_to_accept=[cirq.CZ])
+
+
+# TODO(#5050) Add GlobalPhaseGate
+# Target gates of `cirq_google.GoogleCZTargetGateset`.
+_CZ_TARGET_GATES = [_CZ_FSIM_GATE_FAMILY, _PHASED_XZ_GATE_FAMILY, _MEASUREMENT_GATE_FAMILY]
+# Target gates of `cirq_google.SycamoreTargetGateset`.
+_SYC_TARGET_GATES = [_SYC_FSIM_GATE_FAMILY, _PHASED_XZ_GATE_FAMILY, _MEASUREMENT_GATE_FAMILY]
+# Target gates of `cirq.SqrtIswapTargetGateset`
+_SQRT_ISWAP_TARGET_GATES = [
+    _SQRT_ISWAP_FSIM_GATE_FAMILY,
+    _PHASED_XZ_GATE_FAMILY,
+    _MEASUREMENT_GATE_FAMILY,
+]
+
 
 # Families of gates which can be applied to any subset of valid qubits.
-_VARIADIC_GATE_FAMILIES = [MEASUREMENT_GATE_FAMILY, WAIT_GATE_FAMILY]
+_VARIADIC_GATE_FAMILIES = [_MEASUREMENT_GATE_FAMILY, _WAIT_GATE_FAMILY]
 
 
 def _validate_device_specification(proto: v2.device_pb2.DeviceSpecification) -> None:
@@ -115,19 +135,19 @@ def _build_gateset_and_gate_durations(
         cirq_gates: List[Union[Type[cirq.Gate], cirq.Gate, cirq.GateFamily]] = []
 
         if gate_name == 'syc':
-            cirq_gates = [ops.FSimGateFamily(gates_to_accept=[ops.SYC])]
+            cirq_gates = [_SYC_FSIM_GATE_FAMILY]
         elif gate_name == 'sqrt_iswap':
-            cirq_gates = [ops.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP])]
+            cirq_gates = [_SQRT_ISWAP_FSIM_GATE_FAMILY]
         elif gate_name == 'sqrt_iswap_inv':
-            cirq_gates = [ops.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV])]
+            cirq_gates = [_SQRT_ISWAP_INV_FSIM_GATE_FAMILY]
         elif gate_name == 'cz':
-            cirq_gates = [ops.FSimGateFamily(gates_to_accept=[cirq.CZ])]
+            cirq_gates = [_CZ_FSIM_GATE_FAMILY]
         elif gate_name == 'phased_xz':
             cirq_gates = [cirq.PhasedXZGate, cirq.XPowGate, cirq.YPowGate, cirq.PhasedXPowGate]
         elif gate_name == 'virtual_zpow':
-            cirq_gates = [cirq.GateFamily(cirq.ZPowGate, tags_to_ignore=[ops.PhysicalZTag()])]
+            cirq_gates = [_VIRTUAL_ZPOW_GATE_FAMILY]
         elif gate_name == 'physical_zpow':
-            cirq_gates = [cirq.GateFamily(cirq.ZPowGate, tags_to_accept=[ops.PhysicalZTag()])]
+            cirq_gates = [_PHYSICAL_ZPOW_GATE_FAMILY]
         elif gate_name == 'coupler_pulse':
             cirq_gates = [experimental_ops.CouplerPulse]
         elif gate_name == 'meas':
@@ -161,28 +181,27 @@ def _build_gateset_and_gate_durations(
 def _build_compilation_target_gatesets(
     gateset: cirq.Gateset,
 ) -> Sequence[cirq.CompilationTargetGateset]:
-    """Detects compilation target gatesets based on what gates are inside the gateset.
-
-    If a device contains gates which yield multiple compilation target gatesets, the user can only
-    choose one target gateset to compile to. For example, a device may contain both SYC and
-    SQRT_ISWAP gates which yield two separate target gatesets, but a circuit can only be compiled to
-    either SYC or SQRT_ISWAP for its two-qubit gates, not both.
-
-    TODO(#5050) when cirq-google CompilationTargetGateset subclasses are implemented, mention that
-    gates which are part of the gateset but not the compilation target gateset are untouched when
-    compiled.
-    """
-
-    # TODO(#5050) Subclass core CompilationTargetGatesets in cirq-google.
+    """Detects compilation target gatesets based on what gates are inside the gateset."""
 
+    # Include a particular target gateset if the device's gateset contains all required gates of
+    # the target gateset.
+    # Set all remaining gates in the device's gateset as `additional_gates` so that they are not
+    # decomposed in the transformation process.
     target_gatesets: List[cirq.CompilationTargetGateset] = []
-    if cirq.CZ in gateset:
-        target_gatesets.append(cirq.CZTargetGateset())
-    if ops.SYC in gateset:
+    if all(gate_family in gateset.gates for gate_family in _CZ_TARGET_GATES):
+        target_gatesets.append(
+            transformers.GoogleCZTargetGateset(
+                additional_gates=list(gateset.gates - set(_CZ_TARGET_GATES))
+            )
+        )
+    if all(gate_family in gateset.gates for gate_family in _SYC_TARGET_GATES):
+        # TODO(#5050) SycamoreTargetGateset additional gates
         target_gatesets.append(transformers.SycamoreTargetGateset())
-    if cirq.SQRT_ISWAP in gateset:
+    if all(gate_family in gateset.gates for gate_family in _SQRT_ISWAP_TARGET_GATES):
         target_gatesets.append(
-            cirq.SqrtIswapTargetGateset(use_sqrt_iswap_inv=cirq.SQRT_ISWAP_INV in gateset)
+            cirq.SqrtIswapTargetGateset(
+                additional_gates=list(gateset.gates - set(_SQRT_ISWAP_TARGET_GATES))
+            )
         )
 
     return tuple(target_gatesets)
@@ -265,7 +284,7 @@ class GridDevice(cirq.Device):
           transform a circuit to one which only contains gates from a native target gateset
           supported by the device.
         >>> device.metadata.compilation_target_gatesets
-        (...cirq.CZTargetGateset...)
+        (...cirq_google.GoogleCZTargetGateset...)
 
         * Assuming valid CompilationTargetGatesets exist for the device, select the first one and
           use it to transform a circuit to one which only contains gates from a native target
@@ -277,11 +296,18 @@ class GridDevice(cirq.Device):
         >>> print(circuit)
         (5, 1): ───PhXZ(a=0,x=1,z=0)───
 
-    A note about CompilationTargetGatesets:
+    Notes about CompilationTargetGatesets:
 
-    A circuit which contains `cirq.WaitGate`s will be dropped if it is transformed using
-    CompilationTargetGatesets generated by GridDevice. To better control circuit timing, insert
-    WaitGates after the circuit has been transformed.
+    * If a device contains gates which yield multiple compilation target gatesets, the user can only
+      choose one target gateset to compile to. For example, a device may contain both SYC and
+      SQRT_ISWAP gates which yield two separate target gatesets, but a circuit can only be compiled
+      to either SYC or SQRT_ISWAP for its two-qubit gates, not both.
+    * For a given compilation target gateset, gates which are part of the device's gateset but not
+      the target gateset are not decomposed. However, they may still be merged with other gates in
+      the circuit.
+    * A circuit which contains `cirq.WaitGate`s will be dropped if it is transformed using
+      CompilationTargetGatesets generated by GridDevice. To better control circuit timing, insert
+      WaitGates after the circuit has been transformed.
 
     Notes for cirq_google internal implementation:
 
@@ -435,31 +461,34 @@ def _value_equality_values_(self):
 def _set_gate_in_gate_spec(
     gate_spec: v2.device_pb2.GateSpecification, gate_family: cirq.GateFamily
 ) -> None:
-    if gate_family == SYC_GATE_FAMILY:
+    if gate_family == _SYC_GATE_FAMILY or gate_family == _SYC_FSIM_GATE_FAMILY:
         gate_spec.syc.SetInParent()
-    elif gate_family == SQRT_ISWAP_GATE_FAMILY:
+    elif gate_family == _SQRT_ISWAP_GATE_FAMILY or gate_family == _SQRT_ISWAP_FSIM_GATE_FAMILY:
         gate_spec.sqrt_iswap.SetInParent()
-    elif gate_family == SQRT_ISWAP_INV_GATE_FAMILY:
+    elif (
+        gate_family == _SQRT_ISWAP_INV_GATE_FAMILY
+        or gate_family == _SQRT_ISWAP_INV_FSIM_GATE_FAMILY
+    ):
         gate_spec.sqrt_iswap_inv.SetInParent()
-    elif gate_family == CZ_GATE_FAMILY:
+    elif gate_family == _CZ_GATE_FAMILY or gate_family == _CZ_FSIM_GATE_FAMILY:
         gate_spec.cz.SetInParent()
-    elif gate_family == PHASED_XZ_GATE_FAMILY:
+    elif gate_family == _PHASED_XZ_GATE_FAMILY:
         gate_spec.phased_xz.SetInParent()
-    elif gate_family == VIRTUAL_ZPOW_GATE_FAMILY:
+    elif gate_family == _VIRTUAL_ZPOW_GATE_FAMILY:
         gate_spec.virtual_zpow.SetInParent()
-    elif gate_family == PHYSICAL_ZPOW_GATE_FAMILY:
+    elif gate_family == _PHYSICAL_ZPOW_GATE_FAMILY:
         gate_spec.physical_zpow.SetInParent()
-    elif gate_family == COUPLER_PULSE_GATE_FAMILY:
+    elif gate_family == _COUPLER_PULSE_GATE_FAMILY:
         gate_spec.coupler_pulse.SetInParent()
-    elif gate_family == MEASUREMENT_GATE_FAMILY:
+    elif gate_family == _MEASUREMENT_GATE_FAMILY:
         gate_spec.meas.SetInParent()
-    elif gate_family == WAIT_GATE_FAMILY:
+    elif gate_family == _WAIT_GATE_FAMILY:
         gate_spec.wait.SetInParent()
     else:
         raise ValueError(f'Unrecognized gate {gate_family}.')
 
 
-def create_device_specification_proto(
+def _create_device_specification_proto(
     *,
     qubits: Collection[cirq.GridQubit],
     pairs: Collection[Tuple[cirq.GridQubit, cirq.GridQubit]],
@@ -469,6 +498,13 @@ def create_device_specification_proto(
 ) -> v2.device_pb2.DeviceSpecification:
     """Serializes the given device information into a DeviceSpecification proto.
 
+    EXPERIMENTAL: DeviceSpecification serialization API may change.
+
+    This function does not serialize a `GridDevice`. Instead, it only takes a subset of device
+    information sufficient to populate the `DeviceSpecification` proto. This reduces the complexity
+    of constructing `DeviceSpecification` and `GridDevice` on server side by requiring only the bare
+    essential device information.
+
     Args:
         qubits: Collection of qubits available on the device.
         pairs: Collection of bidirectional qubit couplings available on the device.

cirq-google/cirq_google/devices/grid_device_test.py

@@ -129,9 +129,43 @@ def _create_device_spec_with_horizontal_couplings():
     }
 
     expected_target_gatesets = (
-        cirq.CZTargetGateset(),
+        cirq_google.GoogleCZTargetGateset(
+            additional_gates=[
+                cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]),
+                cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP]),
+                cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]),
+                cirq.ops.common_gates.XPowGate,
+                cirq.ops.common_gates.YPowGate,
+                cirq.ops.phased_x_gate.PhasedXPowGate,
+                cirq.GateFamily(
+                    cirq.ops.common_gates.ZPowGate, tags_to_ignore=[cirq_google.PhysicalZTag()]
+                ),
+                cirq.GateFamily(
+                    cirq.ops.common_gates.ZPowGate, tags_to_accept=[cirq_google.PhysicalZTag()]
+                ),
+                cirq_google.experimental.ops.coupler_pulse.CouplerPulse,
+                cirq.ops.wait_gate.WaitGate,
+            ]
+        ),
         cirq_google.SycamoreTargetGateset(),
-        cirq.SqrtIswapTargetGateset(use_sqrt_iswap_inv=True),
+        cirq.SqrtIswapTargetGateset(
+            additional_gates=[
+                cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]),
+                cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]),
+                cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ]),
+                cirq.ops.common_gates.XPowGate,
+                cirq.ops.common_gates.YPowGate,
+                cirq.ops.phased_x_gate.PhasedXPowGate,
+                cirq.GateFamily(
+                    cirq.ops.common_gates.ZPowGate, tags_to_ignore=[cirq_google.PhysicalZTag()]
+                ),
+                cirq.GateFamily(
+                    cirq.ops.common_gates.ZPowGate, tags_to_accept=[cirq_google.PhysicalZTag()]
+                ),
+                cirq_google.experimental.ops.coupler_pulse.CouplerPulse,
+                cirq.ops.wait_gate.WaitGate,
+            ]
+        ),
     )
 
     return (
@@ -431,7 +465,7 @@ def test_to_proto():
         cirq.GateFamily(cirq.ops.wait_gate.WaitGate): base_duration * 9,
     }
 
-    spec = grid_device.create_device_specification_proto(
+    spec = grid_device._create_device_specification_proto(
         qubits=device_info.grid_qubits,
         pairs=device_info.qubit_pairs,
         gateset=cirq.Gateset(*gate_durations.keys()),
@@ -471,13 +505,13 @@ def test_to_proto():
 )
 def test_to_proto_invalid_input(error_match, qubits, qubit_pairs, gateset, gate_durations):
     with pytest.raises(ValueError, match=error_match):
-        grid_device.create_device_specification_proto(
+        grid_device._create_device_specification_proto(
             qubits=qubits, pairs=qubit_pairs, gateset=gateset, gate_durations=gate_durations
         )
 
 
 def test_to_proto_empty():
-    spec = grid_device.create_device_specification_proto(
+    spec = grid_device._create_device_specification_proto(
         # Qubits are always expected to be set
         qubits=[cirq.GridQubit(0, i) for i in range(5)],
         pairs=[],
@@ -490,3 +524,23 @@ def test_to_proto_empty():
     assert len(device.metadata.qubit_pairs) == 0
     assert device.metadata.gateset == cirq.Gateset()
     assert device.metadata.gate_durations is None
+
+
+def test_to_proto_fsim_gate_family():
+    """Verifies that FSimGateFamilies are serialized correctly."""
+
+    gateset = cirq.Gateset(
+        cirq_google.FSimGateFamily(gates_to_accept=[cirq_google.SYC]),
+        cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP]),
+        cirq_google.FSimGateFamily(gates_to_accept=[cirq.SQRT_ISWAP_INV]),
+        cirq_google.FSimGateFamily(gates_to_accept=[cirq.CZ]),
+    )
+
+    spec = grid_device._create_device_specification_proto(
+        qubits=[cirq.GridQubit(0, 0)], pairs=(), gateset=gateset
+    )
+
+    assert any(gate_spec.HasField('syc') for gate_spec in spec.valid_gates)
+    assert any(gate_spec.HasField('sqrt_iswap') for gate_spec in spec.valid_gates)
+    assert any(gate_spec.HasField('sqrt_iswap_inv') for gate_spec in spec.valid_gates)
+    assert any(gate_spec.HasField('cz') for gate_spec in spec.valid_gates)

cirq-google/cirq_google/devices/known_devices.py

@@ -80,7 +80,7 @@ def _create_grid_device_from_diagram(
             if neighbor > qubit and neighbor in qubit_set:
                 pairs.append((qubit, cast(cirq.GridQubit, neighbor)))
 
-    device_specification = grid_device.create_device_specification_proto(
+    device_specification = grid_device._create_device_specification_proto(
         qubits=qubits, pairs=pairs, gateset=gateset, gate_durations=gate_durations, out=out
     )
     return grid_device.GridDevice.from_proto(device_specification)