fix(port_riscv): use instruction sequences that allow unrestricted jump range

yvt · yvt · commit 07d2e59cc478 · 2020-08-29T19:45:10.000+09:00
diff --git a/src/constance_port_riscv/src/threading/imp.rs b/src/constance_port_riscv/src/threading/imp.rs
@@ -214,7 +214,7 @@ impl State {
                 li a0, {MPIE}
                 csrs mstatus, a0
 
-                j {push_second_level_state_and_dispatch}.dispatch
+                tail {push_second_level_state_and_dispatch}.dispatch
                 ",
                 MAIN_STACK = sym MAIN_STACK,
                 push_second_level_state_and_dispatch =
