feat(test_runner): add new targets qemu_sifive_u_s_rv{32,64}

Author: yvt

.github/workflows/ci.yml

@@ -214,6 +214,10 @@ jobs:
           - { ty: riscv, runner_target: qemu_sifive_u_rv64, runner_args: --arch rv64i+m+a }
           # SiFive U, RV32GC
           - { ty: riscv, runner_target: qemu_sifive_u_rv32, runner_args: "" }
+          # SiFive U, RV64GC, S-mode
+          - { ty: riscv, runner_target: qemu_sifive_u_s_rv64, runner_args: "" }
+          # SiFive U, RV32GC, S-mode
+          - { ty: riscv, runner_target: qemu_sifive_u_s_rv32, runner_args: "" }
           # SiFive E, RV32IMAC
           - { ty: riscv, runner_target: qemu_sifive_e_rv32, runner_args: "" }
           # SiFive E, RV32IA

doc/testing.md

@@ -41,6 +41,7 @@ The following table shows how to run the kernel test suite for each target.
 | RV32GC          | [SiFive U][] (QEMU)                       | `cargo r3test -t qemu_sifive_u_rv32`                      |
 | RV64IMAC        | SiFive U (QEMU)                           | `cargo r3test -t qemu_sifive_u_rv64 -a rv64i+m+a+c`       |
 | RV64GC          | SiFive U (QEMU)                           | `cargo r3test -t qemu_sifive_u_rv64`                      |
+| RV64GC          | SiFive U (S-mode, QEMU)                   | `cargo r3test -t qemu_sifive_u_s_rv64`                    |
 | RV32IMAC        | [RED-V][] (SPI flash XIP)                 | `cargo r3test -t red_v`                                   |
 | RV64GC          | [Maix][] boards (UART ISP)                | `cargo r3test -t maix`                                    |
 

src/r3_port_riscv_test_driver/Cargo.toml

@@ -17,10 +17,18 @@ run = [
     "log",
 ]
 
+# --------------------------------------------------------------------
+
+# Minimal startup code that relies on a bootloader to
+# load all sections and assumes S-mode
+boot-minimal-s = []
+# Use `riscv-rt` for the startup code
 boot-rt = [
     "riscv-rt",
 ]
 
+# --------------------------------------------------------------------
+
 output-rtt = [
     "rtt-target",
 ]
@@ -39,12 +47,16 @@ output-k210-uart = [
 ]
 output-uart = []
 
+# --------------------------------------------------------------------
+
 interrupt-e310x = [
     "e310x",
 ]
 interrupt-u540-qemu = []
 interrupt-k210 = []
 
+# --------------------------------------------------------------------
+
 board-e310x-red-v = [
     "e310x-hal",
 ]
@@ -54,6 +66,13 @@ board-e310x-qemu = [
 board-u540-qemu = []
 board-maix = []
 
+# --------------------------------------------------------------------
+
+timer-clint = []
+timer-sbi = []
+
+# --------------------------------------------------------------------
+
 [dependencies]
 r3_port_riscv = { path = "../r3_port_riscv", optional = true }
 r3_portkit = { path = "../r3_portkit", optional = true }

src/r3_port_riscv_test_driver/src/main.rs

@@ -78,11 +78,53 @@ macro_rules! instantiate_test {
 
         type System = r3_kernel::System<SystemTraits>;
         port::use_port!(unsafe struct SystemTraits);
+
+        #[cfg(feature = "timer-clint")]
+        port::use_mtime!(unsafe impl PortTimer for SystemTraits);
+        #[cfg(feature = "timer-sbi")]
+        port::use_sbi_timer!(unsafe impl PortTimer for SystemTraits);
+
+        impl port::ThreadingOptions for SystemTraits {
+            #[cfg(feature = "boot-minimal-s")]
+            const PRIVILEGE_LEVEL: u8 = port::PRIVILEGE_LEVEL_SUPERVISOR;
+        }
+
         #[cfg(feature = "boot-rt")]
         port::use_rt!(unsafe SystemTraits);
-        port::use_mtime!(unsafe impl PortTimer for SystemTraits);
 
-        impl port::ThreadingOptions for SystemTraits {}
+        #[cfg(feature = "boot-minimal-s")]
+        #[no_mangle]
+        #[naked]
+        extern "C" fn start() {
+            unsafe {
+                core::arch::asm!(
+                    "
+                    # Configure the initial stack
+                    la a0, {MAIN_STACK}
+                    li a1, 8192
+                    andi a0, a0, -16
+                    add sp, a0, a1
+
+                    call {start_kernel}
+                    ",
+                    start_kernel = sym start_kernel,
+                    MAIN_STACK = sym MAIN_STACK,
+                    options(noreturn)
+                );
+            }
+
+            static MAIN_STACK: core::mem::MaybeUninit<[u8; 8192]> = core::mem::MaybeUninit::uninit();
+
+            extern "C" fn start_kernel() {
+                unsafe {
+                    core::arch::asm!(
+                        "csrw stvec, {}",
+                        in(reg) <SystemTraits as port::EntryPoint>::TRAP_HANDLER,
+                    );
+                    <SystemTraits as port::EntryPoint>::start();
+                }
+            }
+        }
 
         #[cfg(feature = "interrupt-e310x")]
         use_interrupt_e310x!(unsafe impl InterruptController for SystemTraits);
@@ -107,6 +149,7 @@ macro_rules! instantiate_test {
             const CONTEXT: usize = 0;
         }
 
+        #[cfg(feature = "timer-clint")]
         impl port::MtimeOptions for SystemTraits {
             const MTIME_PTR: usize = 0x0200_bff8;
 
@@ -130,6 +173,12 @@ macro_rules! instantiate_test {
             const RESET_MTIME: bool = false;
         }
 
+        #[cfg(feature = "timer-sbi")]
+        impl port::SbiTimerOptions for SystemTraits {
+            #[cfg(feature = "board-u540-qemu")]
+            const FREQUENCY: u64 = u540::MTIME_FREQUENCY;
+        }
+
         struct Driver;
 
         #[cfg(feature = "kernel_benchmarks")]
@@ -241,6 +290,23 @@ macro_rules! instantiate_test {
 
             test_case::App::new::<_, Driver>(b)
         }
+
+        /// Like `riscv::interrupt::free` but uses the correct CSR for the
+        /// application's privilege level
+        #[inline]
+        fn with_cpu_lock(f: impl FnOnce()) {
+            use r3::{prelude::*, kernel::CpuLockError};
+            struct Guard(Result<(), CpuLockError>);
+            let _guard = Guard(System::acquire_cpu_lock());
+            f();
+            impl Drop for Guard {
+                fn drop(&mut self) {
+                    if self.0.is_ok() {
+                        let _ = unsafe { System::release_cpu_lock() };
+                    }
+                }
+            }
+        }
     };
 
     () => {}
@@ -272,3 +338,14 @@ mod driver_kernel_tests {
 fn main() {
     panic!("This executable should not be invoked directly");
 }
+
+// Wildcard imports take less precedence
+#[allow(unused_imports)]
+use default_impl::*;
+#[allow(dead_code)]
+mod default_impl {
+    #[track_caller]
+    fn with_cpu_lock(_: impl FnOnce()) {
+        unreachable!();
+    }
+}

src/r3_port_riscv_test_driver/src/uart_u540.rs

@@ -1,22 +1,21 @@
 //! The UART driver compatible with QEMU `sifive_u` machine
 //! (RISC-V Board compatible with SiFive U SDK).
 use core::fmt::{self, Write};
-use riscv::interrupt;
 
 pub fn stdout_write_str(s: &str) {
-    interrupt::free(|_| {
+    crate::with_cpu_lock(|| {
         let _ = SerialWrapper(0x10010000 as *mut u32).write_str(s);
     });
 }
 
 pub fn stdout_write_fmt(args: fmt::Arguments<'_>) {
-    interrupt::free(|_| {
+    crate::with_cpu_lock(|| {
         let _ = SerialWrapper(0x10010000 as *mut u32).write_fmt(args);
     });
 }
 
 pub fn stderr_write_fmt(args: fmt::Arguments<'_>) {
-    interrupt::free(|_| {
+    crate::with_cpu_lock(|| {
         let _ = SerialWrapper(0x10011000 as *mut u32).write_fmt(args);
     });
 }

src/r3_test_runner/src/targets.rs

@@ -67,6 +67,57 @@ impl LinkerScripts {
             generated_files: vec![("memory.x".to_owned(), memory_definition)],
         }
     }
+
+    /// Create `LinkerScripts` to define some standard sections, which are to
+    /// be included in the final image header and initialized by a section-aware
+    /// loader. Symbol `start` is treated as the entry point.
+    fn standard(base_address: u64) -> Self {
+        let link = r#"
+            ENTRY(start);
+
+            SECTIONS
+            {
+              . = BASE_ADDRESS;
+
+              .text :
+              {
+                *(.text .text.*);
+                . = ALIGN(4);
+                __etext = .;
+              }
+
+              .rodata __etext : ALIGN(4)
+              {
+                *(.rodata .rodata.*);
+                . = ALIGN(4);
+              }
+
+              .data : ALIGN(4)
+              {
+                *(.data .data.*);
+                . = ALIGN(4);
+              }
+
+              __sidata = LOADADDR(.data);
+
+              .bss : ALIGN(4)
+              {
+                __sbss = .;
+                *(.bss .bss.*);
+                . = ALIGN(4);
+                __ebss = .;
+              }
+            }
+        "#
+        .to_owned();
+
+        let link = link.replace("BASE_ADDRESS", &base_address.to_string());
+
+        Self {
+            inputs: vec!["link.x".to_owned()],
+            generated_files: vec![("link.x".to_owned(), link)],
+        }
+    }
 }
 
 pub trait DebugProbe: Send {
@@ -90,6 +141,14 @@ pub static TARGETS: &[(&str, &dyn Target)] = &[
     ("qemu_sifive_e_rv64", &qemu::riscv::QemuSiFiveE(Xlen::_64)),
     ("qemu_sifive_u_rv32", &qemu::riscv::QemuSiFiveU(Xlen::_32)),
     ("qemu_sifive_u_rv64", &qemu::riscv::QemuSiFiveU(Xlen::_64)),
+    (
+        "qemu_sifive_u_s_rv32",
+        &qemu::riscv::QemuSiFiveUModeS(Xlen::_32),
+    ),
+    (
+        "qemu_sifive_u_s_rv64",
+        &qemu::riscv::QemuSiFiveUModeS(Xlen::_64),
+    ),
     ("red_v", &jlink::RedV),
     ("maix", &kflash::Maix),
     ("rp_pico", &rp_pico::RaspberryPiPico),

src/r3_test_runner/src/targets/jlink.rs

@@ -31,6 +31,7 @@ impl Target for RedV {
             "boot-rt".to_owned(),
             "output-rtt".to_owned(),
             "interrupt-e310x".to_owned(),
+            "timer-clint".to_owned(),
             "board-e310x-red-v".to_owned(),
             "r3_port_riscv/emulate-lr-sc".to_owned(),
         ]

src/r3_test_runner/src/targets/kflash.rs

@@ -30,6 +30,7 @@ impl Target for Maix {
             "boot-rt".to_owned(),
             "output-k210-uart".to_owned(),
             "interrupt-k210".to_owned(),
+            "timer-clint".to_owned(),
             "board-maix".to_owned(),
             "r3_port_riscv/maintain-pie".to_owned(),
         ]

src/r3_test_runner/src/targets/qemu/riscv.rs

@@ -22,6 +22,7 @@ impl Target for QemuSiFiveE {
             "boot-rt".to_owned(),
             "output-e310x-uart".to_owned(),
             "interrupt-e310x".to_owned(),
+            "timer-clint".to_owned(),
             "board-e310x-qemu".to_owned(),
         ]
     }
@@ -92,6 +93,7 @@ impl Target for QemuSiFiveU {
             "boot-rt".to_owned(),
             "output-u540-uart".to_owned(),
             "interrupt-u540-qemu".to_owned(),
+            "timer-clint".to_owned(),
             "board-u540-qemu".to_owned(),
         ]
     }
@@ -117,6 +119,7 @@ impl Target for QemuSiFiveU {
             .to_owned(),
         )
     }
+
     fn connect(&self) -> Pin<Box<dyn Future<Output = Result<Box<dyn DebugProbe>>>>> {
         let xlen = self.0;
         Box::pin(async move {
@@ -144,3 +147,57 @@ impl Target for QemuSiFiveU {
         })
     }
 }
+
+/// The RISC-V board compatible with SiFive U SDK on QEMU, using a bootloader to
+/// run the kernel in S-mode
+pub struct QemuSiFiveUModeS(pub Xlen);
+
+impl Target for QemuSiFiveUModeS {
+    fn target_arch(&self) -> Arch {
+        match self.0 {
+            Xlen::_32 => Arch::RV32GC,
+            Xlen::_64 => Arch::RV64GC,
+        }
+    }
+
+    fn cargo_features(&self) -> Vec<String> {
+        vec![
+            "boot-minimal-s".to_owned(),
+            "output-u540-uart".to_owned(),
+            "interrupt-u540-qemu".to_owned(),
+            "timer-sbi".to_owned(),
+            "board-u540-qemu".to_owned(),
+        ]
+    }
+
+    fn linker_scripts(&self) -> LinkerScripts {
+        // Somewhere near `0x80000000` is occupied by the bootloader (the
+        // default `-bios`), so avoid that
+        LinkerScripts::standard(0x80100000)
+    }
+
+    fn connect(&self) -> Pin<Box<dyn Future<Output = Result<Box<dyn DebugProbe>>>>> {
+        let xlen = self.0;
+        Box::pin(async move {
+            Ok(Box::new(QemuDebugProbe::new(
+                match xlen {
+                    Xlen::_32 => "qemu-system-riscv32",
+                    Xlen::_64 => "qemu-system-riscv64",
+                },
+                &[
+                    "-machine",
+                    "sifive_u",
+                    // UART0 → stdout
+                    "-serial",
+                    "file:/dev/stdout",
+                    // UART1 → stderr
+                    "-serial",
+                    "file:/dev/stderr",
+                    // Disable monitor
+                    "-monitor",
+                    "none",
+                ],
+            )) as Box<dyn DebugProbe>)
+        })
+    }
+}