feat(port_riscv): add use_sbi_timer!

yvt · yvt · commit fa3fea049db8 · 2022-01-11T20:51:10.000+09:00
diff --git a/src/r3_port_riscv/CHANGELOG.md b/src/r3_port_riscv/CHANGELOG.md
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Added
 
 - The new option `ThreadingOptions::PRIVILEGE_LEVEL` allows for running the kernel in other privilege levels than M-mode.
+- `use_sbi_timer!` can be used to install a timer driver based on [the RISC-V Supervisor Binary Interface](https://github.com/riscv-non-isa/riscv-sbi-doc).
 
 ### Changed
 
diff --git a/src/r3_port_riscv/src/lib.rs b/src/r3_port_riscv/src/lib.rs
@@ -75,9 +75,17 @@ pub mod mtime {
     pub mod imp;
 }
 
+/// The SBI-based timer driver.
+#[doc(hidden)]
+pub mod sbi_timer {
+    pub mod cfg;
+    pub mod imp;
+}
+
 pub use self::mtime::cfg::*;
 pub use self::plic::cfg::*;
 pub use self::rt::cfg::*;
+pub use self::sbi_timer::cfg::*;
 pub use self::threading::cfg::*;
 
 /// Defines the entry points of a port instantiation. Implemented by
@@ -110,7 +118,7 @@ pub trait EntryPoint {
 }
 
 /// An abstract inferface to a port timer driver. Implemented by
-/// [`use_mtime!`].
+/// [`use_mtime!`] and [`use_sbi_timer!`].
 pub trait Timer {
     /// Initialize the driver. This will be called just before entering
     /// [`PortToKernel::boot`].
diff --git a/src/r3_port_riscv/src/sbi_timer/cfg.rs b/src/r3_port_riscv/src/sbi_timer/cfg.rs
@@ -0,0 +1,147 @@
+//! The public interface for the SBI-based timer driver.
+use r3_core::kernel::InterruptNum;
+
+/// Attach the implementation of [`PortTimer`] based on [the RISC-V Supervisor
+/// Binary Interface][1] Timer Extension (EID #0x54494D45 "TIME") and `time[h]`
+/// CSR to a given kernel trait type.
+/// This macro also implements [`Timer`] on the system type.
+/// **Requires [`SbiTimerOptions`].**
+///
+/// [1]: https://github.com/riscv-non-isa/riscv-sbi-doc
+/// [`PortTimer`]: r3_kernel::PortTimer
+/// [`Timer`]: crate::Timer
+///
+/// You should do the following:
+///
+///  - Implement [`SbiTimerOptions`] on the system type `$Traits`.
+///  - Call `$Traits::configure_timer()` in your configuration function.
+///    See the following example.
+///
+/// ```rust,ignore
+/// r3_port_riscv::use_sbi_timer!(unsafe impl PortTimer for System);
+///
+/// impl r3_port_riscv::SbiTimerOptions for System {
+///     const FREQUENCY: u64 = 1_000_000;
+/// }
+///
+/// const fn configure_app(b: &mut CfgBuilder<System>) -> Objects {
+///     System::configure_timer(b);
+///     /* ... */
+/// }
+/// ```
+///
+/// # Safety
+///
+///  - `SbiTimerOptions` must be configured correctly.
+///
+#[macro_export]
+macro_rules! use_sbi_timer {
+    (unsafe impl PortTimer for $Traits:ty) => {
+        const _: () = {
+            use $crate::r3_core::{
+                kernel::{traits, Cfg},
+                utils::Init,
+            };
+            use $crate::r3_kernel::{PortTimer, System, UTicks};
+            use $crate::r3_portkit::tickless;
+            use $crate::{sbi_timer, SbiTimerOptions, Timer};
+
+            impl PortTimer for $Traits {
+                const MAX_TICK_COUNT: UTicks = u32::MAX;
+                const MAX_TIMEOUT: UTicks = u32::MAX;
+
+                unsafe fn tick_count() -> UTicks {
+                    // Safety: We are just forwarding the call
+                    unsafe { sbi_timer::imp::tick_count::<Self>() }
+                }
+
+                unsafe fn pend_tick() {
+                    // Safety: We are just forwarding the call
+                    unsafe { sbi_timer::imp::pend_tick::<Self>() }
+                }
+
+                unsafe fn pend_tick_after(tick_count_delta: UTicks) {
+                    // Safety: We are just forwarding the call
+                    unsafe { sbi_timer::imp::pend_tick_after::<Self>(tick_count_delta) }
+                }
+            }
+
+            impl Timer for $Traits {
+                unsafe fn init() {
+                    unsafe { sbi_timer::imp::init::<Self>() }
+                }
+            }
+
+            const TICKLESS_CFG: tickless::TicklessCfg =
+                match tickless::TicklessCfg::new(tickless::TicklessOptions {
+                    hw_freq_num: <$Traits as SbiTimerOptions>::FREQUENCY,
+                    hw_freq_denom: <$Traits as SbiTimerOptions>::FREQUENCY_DENOMINATOR,
+                    hw_headroom_ticks: <$Traits as SbiTimerOptions>::HEADROOM,
+                    // `stime` is a 64-bit free-running counter and it is
+                    // expensive to create a 32-bit timer with an arbitrary
+                    // period out of it.
+                    force_full_hw_period: true,
+                    // Clearing `stime` is not possible, so we must record the
+                    // starting value of `stime` by calling `reset`.
+                    resettable: true,
+                }) {
+                    Ok(x) => x,
+                    Err(e) => e.panic(),
+                };
+
+            static mut TIMER_STATE: tickless::TicklessState<TICKLESS_CFG> = Init::INIT;
+
+            // Safety: Only `use_sbi_timer!` is allowed to `impl` this
+            unsafe impl sbi_timer::imp::TimerInstance for $Traits {
+                const TICKLESS_CFG: tickless::TicklessCfg = TICKLESS_CFG;
+
+                type TicklessState = tickless::TicklessState<TICKLESS_CFG>;
+
+                fn tickless_state() -> *mut Self::TicklessState {
+                    unsafe { core::ptr::addr_of_mut!(TIMER_STATE) }
+                }
+            }
+
+            impl $Traits {
+                pub const fn configure_timer<C>(b: &mut Cfg<C>)
+                where
+                    C: ~const traits::CfgInterruptLine<System = System<Self>>,
+                {
+                    sbi_timer::imp::configure(b);
+                }
+            }
+        };
+    };
+}
+
+/// The options for [`use_sbi_timer!`].
+pub trait SbiTimerOptions {
+    /// The numerator of the effective timer clock rate of the dual timer.
+    const FREQUENCY: u64;
+
+    /// The denominator of the effective timer clock rate of the dual timer.
+    /// Defaults to `1`.
+    const FREQUENCY_DENOMINATOR: u64 = 1;
+
+    /// The maximum permissible timer interrupt latency, measured in hardware
+    /// timer cycles.
+    ///
+    /// Defaults to `min(FREQUENCY * 60 / FREQUENCY_DENOMINATOR, 0x40000000)`.
+    const HEADROOM: u32 = min128(
+        Self::FREQUENCY as u128 * 60 / Self::FREQUENCY_DENOMINATOR as u128,
+        0x40000000,
+    ) as u32;
+
+    /// The timer's interrupt number. Defaults to [`INTERRUPT_TIMER`].
+    ///
+    /// [`INTERRUPT_TIMER`]: crate::INTERRUPT_TIMER
+    const INTERRUPT_NUM: InterruptNum = crate::INTERRUPT_TIMER;
+}
+
+const fn min128(x: u128, y: u128) -> u128 {
+    if x < y {
+        x
+    } else {
+        y
+    }
+}
diff --git a/src/r3_port_riscv/src/sbi_timer/imp.rs b/src/r3_port_riscv/src/sbi_timer/imp.rs
@@ -0,0 +1,201 @@
+//! The implementation of the SBI-based timer driver.
+use core::arch::asm;
+use r3_core::kernel::{traits, Cfg, StaticInterruptHandler};
+use r3_kernel::{KernelTraits, PortToKernel, System, UTicks};
+use r3_portkit::tickless::{TicklessCfg, TicklessStateTrait};
+
+use crate::sbi_timer::cfg::SbiTimerOptions;
+
+/// Implemented on a system type by [`use_sbi_timer!`].
+///
+/// # Safety
+///
+/// Only meant to be implemented by [`use_sbi_timer!`].
+pub unsafe trait TimerInstance: KernelTraits + SbiTimerOptions {
+    // FIXME: Specifying `TicklessCfg::new(...)` here causes a "cycle
+    //        detected" error
+    const TICKLESS_CFG: TicklessCfg;
+
+    // FIXME: Specifying `TicklessState<{ Self::TICKLESS_CFG }>` here
+    //        fails with an error message similar to
+    //        <https://github.com/rust-lang/rust/issues/72821>
+    type TicklessState: TicklessStateTrait;
+
+    fn tickless_state() -> *mut Self::TicklessState;
+}
+
+#[cfg(any(
+    target_arch = "riscv32",
+    target_arch = "riscv64",
+    target_arch = "riscv128"
+))]
+trait TimerInstanceExt: TimerInstance {
+    #[inline(always)]
+    fn time_lo() -> usize {
+        let read: usize;
+        unsafe { asm!("csrr {read}, time", read = lateout(reg) read) };
+        read
+    }
+
+    #[cfg(target_arch = "riscv32")]
+    #[inline(always)]
+    fn time_hi() -> usize {
+        let read: usize;
+        unsafe { asm!("csrr {read}, timeh", read = lateout(reg) read) };
+        read
+    }
+
+    #[inline(always)]
+    #[cfg(target_arch = "riscv32")]
+    fn set_timecmp(value: u64) {
+        unsafe {
+            asm!(
+                "ecall",
+                inout("a0") value as u32 => _,  // param0 => error
+                inout("a1") (value >> 32) as u32 => _, // param => value
+                out("a2") _,
+                out("a3") _,
+                out("a4") _,
+                out("a5") _,
+                inout("a6") 0 => _, //fid
+                inout("a7") 0x54494D45 => _, // eid
+            )
+        };
+    }
+
+    #[inline(always)]
+    #[cfg(not(target_arch = "riscv32"))]
+    fn set_timecmp(value: u64) {
+        unsafe {
+            asm!(
+                "ecall",
+                inout("a0") value as usize => _,  // param0 => error
+                out("a1") _,
+                out("a2") _,
+                out("a3") _,
+                out("a4") _,
+                out("a5") _,
+                inout("a6") 0 => _, //fid
+                inout("a7") 0x54494D45 => _, // eid
+            )
+        };
+    }
+
+    #[cfg(not(target_arch = "riscv32"))]
+    #[inline(always)]
+    fn time() -> u64 {
+        Self::time_lo() as u64
+    }
+
+    #[cfg(target_arch = "riscv32")]
+    #[inline(always)]
+    fn time() -> u64 {
+        loop {
+            let hi1 = Self::time_hi();
+            let lo = Self::time_lo();
+            let hi2 = Self::time_hi();
+            if hi1 == hi2 {
+                return lo as u64 | ((hi2 as u64) << 32);
+            }
+        }
+    }
+}
+#[cfg(not(any(
+    target_arch = "riscv32",
+    target_arch = "riscv64",
+    target_arch = "riscv128"
+)))]
+trait TimerInstanceExt: TimerInstance {
+    fn time_lo() -> usize {
+        unimplemented!("target mismatch")
+    }
+
+    fn set_timecmp(value: u64) {
+        unimplemented!("target mismatch")
+    }
+
+    fn time() -> u64 {
+        unimplemented!("target mismatch")
+    }
+}
+impl<T: TimerInstance> TimerInstanceExt for T {}
+
+/// The configuration function.
+pub const fn configure<C, Traits: TimerInstance>(b: &mut Cfg<C>)
+where
+    C: ~const traits::CfgInterruptLine<System = System<Traits>>,
+{
+    StaticInterruptHandler::define()
+        .line(Traits::INTERRUPT_NUM)
+        .start(handle_tick::<Traits>)
+        .finish(b);
+}
+
+/// Implements [`crate::Timer::init`]
+#[inline]
+pub fn init<Traits: TimerInstance>() {
+    let tcfg = &Traits::TICKLESS_CFG;
+
+    // Safety: No context switching during boot
+    let tstate = unsafe { &mut *Traits::tickless_state() };
+
+    tstate.reset(tcfg, Traits::time_lo() as u32);
+}
+
+/// Implements [`r3_kernel::PortTimer::tick_count`]
+///
+/// # Safety
+///
+/// Only meant to be referenced by `use_sbi_timer!`.
+pub unsafe fn tick_count<Traits: TimerInstance>() -> UTicks {
+    let tcfg = &Traits::TICKLESS_CFG;
+
+    let hw_tick_count = Traits::time_lo() as u32;
+
+    // Safety: CPU Lock protects it from concurrent access
+    let tstate = unsafe { &mut *Traits::tickless_state() };
+    tstate.tick_count(tcfg, hw_tick_count)
+}
+
+/// Implements [`r3_kernel::PortTimer::pend_tick`]
+///
+/// # Safety
+///
+/// Only meant to be referenced by `use_sbi_timer!`.
+pub unsafe fn pend_tick<Traits: TimerInstance>() {
+    Traits::set_timecmp(0);
+}
+
+/// Implements [`r3_kernel::PortTimer::pend_tick_after`]
+///
+/// # Safety
+///
+/// Only meant to be referenced by `use_sbi_timer!`.
+pub unsafe fn pend_tick_after<Traits: TimerInstance>(tick_count_delta: UTicks) {
+    let tcfg = &Traits::TICKLESS_CFG;
+    // Safety: CPU Lock protects it from concurrent access
+    let tstate = unsafe { &mut *Traits::tickless_state() };
+
+    let cur_hw_tick_count = Traits::time();
+    let hw_ticks = tstate
+        .mark_reference_and_measure(tcfg, cur_hw_tick_count as u32, tick_count_delta)
+        .hw_ticks;
+
+    let next_hw_tick_count = cur_hw_tick_count + hw_ticks as u64;
+
+    Traits::set_timecmp(next_hw_tick_count);
+}
+
+#[inline]
+fn handle_tick<Traits: TimerInstance>(_: usize) {
+    let tcfg = &Traits::TICKLESS_CFG;
+
+    // Safety: CPU Lock protects it from concurrent access
+    let tstate = unsafe { &mut *Traits::tickless_state() };
+
+    let cur_hw_tick_count = Traits::time_lo() as u32;
+    tstate.mark_reference(tcfg, cur_hw_tick_count);
+
+    // Safety: CPU Lock inactive, an interrupt context
+    unsafe { Traits::timer_tick() };
+}
