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Commit 7d09664

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fw
1 parent 116b790 commit 7d09664

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3 files changed

+2
-4
lines changed

3 files changed

+2
-4
lines changed

libr/core/anal_tp.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -320,7 +320,6 @@ static bool type_trace_op(TypeTrace *trace, REsil *esil, RAnalOp *op) {
320320
return false;
321321
}
322322
trace->cc = 0;
323-
324323
RRegItem *ri = r_reg_get (trace->reg, "PC", -1);
325324
if (ri) {
326325
const bool suc = r_esil_reg_write_silent (esil, ri->name, op->addr + op->size);

libr/core/cmd_anal.inc.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7224,8 +7224,8 @@ void cmd_anal_reg(RCore *core, const char *str) {
72247224

72257225
#if USE_NEW_ESIL
72267226
R_API int r_core_esil_step(RCore *core, ut64 until_addr, const char *until_expr, ut64 *prev_addr, bool stepOver) {
7227-
const bool is_x86 = r_str_startswith (r_config_get (core->config, "asm.arch"), "x86");
7228-
const bool breakoninvalid = r_config_get_b (core->config, "esil.breakoninvalid");
7227+
// const bool is_x86 = r_str_startswith (r_config_get (core->config, "asm.arch"), "x86");
7228+
// const bool breakoninvalid = r_config_get_b (core->config, "esil.breakoninvalid");
72297229
const int esiltimeout = r_config_get_i (core->config, "esil.timeout");
72307230
int ret = true;
72317231
ut64 startTime = 0;

libr/core/core_esil.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,6 @@ static bool core_esil_mem_read (void *core, ut64 addr, ut8 *buf, int len) {
8585
if (!addr && c->esil.cfg & R_CORE_ESIL_NONULL) {
8686
return false;
8787
}
88-
8988
if (c->esil.cmd_mdev && c->esil.mdev_range && r_str_range_in (c->esil.mdev_range, addr)) {
9089
r_core_cmdf (c, "%s %"PFMT64d" 0", c->esil.cmd_mdev, c->esil.old_pc);
9190
return c->num->value;

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