|
| 1 | +package memories |
| 2 | + |
| 3 | +import org.scalatest.funspec.AnyFunSpec |
| 4 | +import org.scalatest.matchers.must.Matchers |
| 5 | + |
| 6 | +import tywaves.simulator._ |
| 7 | +import tywaves.simulator.simulatorSettings._ |
| 8 | +import chisel3._ |
| 9 | + |
| 10 | +class BlockMemTest extends AnyFunSpec with Matchers { |
| 11 | + describe("TywavesSimulator") { |
| 12 | + import TywavesSimulator._ |
| 13 | + |
| 14 | + it("runs BlockMem of UInt8") { |
| 15 | + val t = UInt(8.W) |
| 16 | + simulate(new BlockMem(15, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_uint8")(dut => |
| 17 | + dut.clock.step(2) |
| 18 | + ) |
| 19 | + } |
| 20 | + |
| 21 | + it("runs BlockMem of Bundle") { |
| 22 | + |
| 23 | + class ComplexElement extends Bundle { |
| 24 | + val a = new Bundle { |
| 25 | + val subA1 = UInt(8.W) |
| 26 | + val subA2 = SInt(8.W) |
| 27 | + } |
| 28 | + val payload = Bits(8.W) |
| 29 | + } |
| 30 | + |
| 31 | + val t = new ComplexElement |
| 32 | + simulate( |
| 33 | + new BlockMem(4, t), |
| 34 | + Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile("workdir")), |
| 35 | + simName = "runs_mem_bundle", |
| 36 | + )(dut => dut.clock.step(2)) |
| 37 | + } |
| 38 | + |
| 39 | + it("runs BlockMem of Vec") { |
| 40 | + val t = Vec(4, UInt(8.W)) |
| 41 | + simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_vec")(dut => |
| 42 | + dut.clock.step(2) |
| 43 | + ) |
| 44 | + } |
| 45 | + |
| 46 | + it("runs BlockMem of Enum") { |
| 47 | + object SelType extends ChiselEnum { val A, B, C = Value } |
| 48 | + val t = SelType() |
| 49 | + simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum")(dut => |
| 50 | + dut.clock.step(2) |
| 51 | + ) |
| 52 | + } |
| 53 | + |
| 54 | + it("runs BlockMem of Enum in Bundle") { |
| 55 | + object SelType extends ChiselEnum { val A, B, C = Value } |
| 56 | + class ComplexElement extends Bundle { |
| 57 | + val sel = SelType() |
| 58 | + val payload = Bits(8.W) |
| 59 | + } |
| 60 | + |
| 61 | + val t = new ComplexElement |
| 62 | + simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_bundle")(dut => |
| 63 | + dut.clock.step(2) |
| 64 | + ) |
| 65 | + } |
| 66 | + |
| 67 | + it("runs BlockMem of Enum in Vec") { |
| 68 | + object SelType extends ChiselEnum { val A, B, C = Value } |
| 69 | + val t = Vec(4, SelType()) |
| 70 | + simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_vec")(dut => |
| 71 | + dut.clock.step(2) |
| 72 | + ) |
| 73 | + } |
| 74 | + |
| 75 | + it("runs BlockMem of Enum in 2D-Vec") { |
| 76 | + object SelType extends ChiselEnum { val A, B, C = Value } |
| 77 | + val t = Vec(4, Vec(2, SelType())) |
| 78 | + simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_2d_vec")(dut => |
| 79 | + dut.clock.step(2) |
| 80 | + ) |
| 81 | + } |
| 82 | + |
| 83 | + } |
| 84 | +} |
0 commit comments