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ramelonirameloni
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Fix bug for submodule instances: multiple sub-instances of the same module type
1 parent 1d125c7 commit 9033ec2

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11 files changed

+74
-32
lines changed

11 files changed

+74
-32
lines changed

‎src/main/scala/chisel3/tywaves/circuitparser/ChiselIRParser.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ class ChiselIRParser
6565

6666
// Parse generic info and create an ID for the port
6767
val (name, info, dir) = (portData.toNamed.name, port.sourceInfo, port.dir)
68-
val elId = this.createId(info, Some(name))
68+
val elId = this.createId(info, Some(name + scope))
6969

7070
ports.put(
7171
elId,
@@ -161,8 +161,8 @@ class ChiselIRParser
161161
case _ =>
162162
// TODO: other cases need to be implemented. For now, simply add the element to the map
163163
if (hwType == HardwareType("Port", Some(dataType.getWidth)))
164-
flattenedPorts.put(elId.addName(name.name), (name, dir, hwType, Type(dataType.typeName)))
165-
allElements.put(elId.addName(name.name), (name, dir, Type(dataType.typeName)))
164+
flattenedPorts.put(elId.addName(name.name + parentModule), (name, dir, hwType, Type(dataType.typeName)))
165+
allElements.put(elId.addName(name.name + parentModule), (name, dir, Type(dataType.typeName)))
166166
case _ => throw new Exception(s"Failed to parse type $dataType. Unknown type.")
167167
}
168168
// ??? // TODO: Implement for Data types

‎src/main/scala/chisel3/tywaves/circuitparser/CircuitParser.scala‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,13 +52,14 @@ trait CircuitParser[T, ModuleT, PortT, AggregateT, ElementT, BodyStatementT] {
5252
case chisel: chisel3.Record => chisel.className
5353
case aggr: chisel3.Aggregate => aggr.typeName
5454
}
55-
if (hwType == HardwareType("Port", Some(this.getWidth(agg))))
55+
if (hwType == HardwareType("Port", Some(this.getWidth(agg)))) {
5656
flattenedPorts.put(
57-
elId.addName(name.name),
57+
elId.addName(name.name + parentModule),
5858
(name.addTywaveScope(parentModule), dir, hwType, Type(aggString)),
5959
)
60+
}
6061

61-
allElements.put(elId.addName(name.name), (name.addTywaveScope(parentModule), dir, Type(aggString)))
62+
allElements.put(elId.addName(name.name + parentModule), (name.addTywaveScope(parentModule), dir, Type(aggString)))
6263
}
6364

6465
def parseElement(

‎src/main/scala/chisel3/tywaves/circuitparser/FirrtlIRParser.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ class FirrtlIRParser
3131
override def parseModule(firrtlModule: firrtlIR.DefModule): Unit = {
3232
// Parse generic info and create an ID for the module
3333
val (name, info) = (firrtlModule.name, firrtlModule.info)
34-
val elId = this.createId(info)
34+
val elId = this.createId(info, Some(name))
3535

3636
modules.put(elId, (Name(name, "root", "root"), firrtlModule)) // Add the module and its name
3737

@@ -52,7 +52,7 @@ class FirrtlIRParser
5252
override def parsePort(scope: String, port: firrtlIR.Port, parentModule: String): Unit = {
5353
// Parse generic info and create an ID for the port
5454
val (name, info, dir, firrtlType) = (port.name, port.info, port.direction, port.tpe)
55-
val elId = this.createId(info, Some(name))
55+
val elId = this.createId(info, Some(name + scope))
5656

5757
ports.put(
5858
elId,
@@ -133,8 +133,8 @@ class FirrtlIRParser
133133
case ClockType | AsyncResetType | ResetType |
134134
UIntType(_) | SIntType(_) | AnalogType(_) =>
135135
if (hwType == HardwareType("Port", None))
136-
flattenedPorts.put(elId.addName(name.name), (name, dir, hwType, Type(firrtlType.toString)))
137-
allElements.put(elId.addName(name.name), (name, dir, Type(firrtlType.toString)))
136+
flattenedPorts.put(elId.addName(name.name + parentModule), (name, dir, hwType, Type(firrtlType.toString)))
137+
allElements.put(elId.addName(name.name + parentModule), (name, dir, Type(firrtlType.toString)))
138138
case _ => throw new Exception(s"Failed to parse type $firrtlType. Unknown type.")
139139
}
140140
}

‎src/main/scala/tywaves/circuitmapper/MapChiselToVcd.scala‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -209,7 +209,7 @@ class MapChiselToVcd[T <: RawModule](generateModule: () => T, private val workin
209209

210210
}.unzip
211211
val childScopes = findChildScopes(circuitChiselIR.name, groupIrPerElement)
212-
val scopes = Seq(tywaves_symbol_table.Scope(name = dutName, childVariables.toSeq, childScopes))
212+
val scopes = Seq(tywaves_symbol_table.Scope(name = dutName, childVariables.toSeq, childScopes))
213213
// Finalize the scopes -> mergeScopes(scope) is not needed anymore
214214
val finalScopes = cleanFromFlattenedSignals(scopes)
215215

@@ -369,7 +369,7 @@ class MapChiselToVcd[T <: RawModule](generateModule: () => T, private val workin
369369

370370
val childScopeNames = gDebugIRParser.modules.filter {
371371
case (_, Name(_, _, tywaveScope)) =>
372-
tywaveScope == parentScope
372+
tywaveScope == parentScope
373373
}.map { case (_, Name(name, scope, _)) => (name, scope) }.toSet
374374

375375
childScopeNames.foreach(println)
@@ -393,7 +393,11 @@ class MapChiselToVcd[T <: RawModule](generateModule: () => T, private val workin
393393
.map { case (variableOpt, scopes) => (variableOpt.get, scopes) }
394394

395395
}.unzip
396-
childScopes :+= tywaves_symbol_table.Scope(instanceName, childVariables.toSeq, findChildScopes(childScopeName, groupIrPerElement))
396+
childScopes :+= tywaves_symbol_table.Scope(
397+
instanceName,
398+
childVariables.toSeq,
399+
findChildScopes(childScopeName, groupIrPerElement),
400+
)
397401
}
398402
childScopes
399403
// val (childVariables, childScopes) = groupIrPerElement.flatMap {

‎src/main/scala/tywaves/circuitmapper/TypedConverter.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ private object TypedConverter {
5050

5151
chiselStage.execute(
5252
args ++ Array("--target-dir", hglddDebugDir),
53-
annotations ++ Seq(circt.stage.FirtoolOption("-g")),
53+
annotations ++ Seq(circt.stage.FirtoolOption("-g"), circt.stage.FirtoolOption("-O=debug")),
5454
// execute returns the passThrough annotations in CIRCT transform stage
5555
)
5656
}

‎src/main/scala/tywaves/hglddparser/DebugIRParser.scala‎

Lines changed: 32 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,21 @@ class DebugIRParser(val workingDir: String, ddFilePath: String) {
9999

100100
val scope =
101101
hglddObject.obj_name.lastIndexOf("_") match {
102-
case -1 => thisChildName.getOrElse("root"); case i => hglddObject.obj_name.substring(0, i)
102+
case -1 => thisChildName.getOrElse("root")
103+
case i =>
104+
// TODO: here the problem, multiple instances are separated by _ + an index
105+
val lastPart = hglddObject.obj_name.substring(i + 1)
106+
107+
val tmpScope = hglddObject.obj_name.substring(0, i)
108+
109+
if (lastPart.forall(Character.isDigit)) {
110+
println("FOUND: " + hglddObject.obj_name)
111+
thisChildName.getOrElse("root")
112+
} else {
113+
println("NOT FOUND: " + s"tmpScope: $tmpScope" + s" hglddObject.obj_name ${hglddObject.obj_name}")
114+
tmpScope
115+
}
116+
103117
}
104118
// Drop the scope from the object name
105119
val obj_name =
@@ -109,17 +123,31 @@ class DebugIRParser(val workingDir: String, ddFilePath: String) {
109123
hglddObject.obj_name.substring(scope.length + 1)
110124

111125
val elId =
112-
createId(fileInfo, hglddObject.hgl_loc, obj_name)
126+
createId(fileInfo, hglddObject.hgl_loc, obj_name + scope)
113127
val parentModule =
114128
hglddObject.obj_name.lastIndexOf("_") match {
115-
case -1 => thisChildParentName.getOrElse("root"); case i => hglddObject.obj_name.substring(0, i)
129+
case -1 => thisChildParentName.getOrElse("root");
130+
case i =>
131+
// TODO: here the problem, multiple instances are separated by _ + an index
132+
val lastPart = hglddObject.obj_name.substring(i + 1)
133+
134+
val tmpScope = hglddObject.obj_name.substring(0, i)
135+
136+
if (lastPart.forall(Character.isDigit)) {
137+
println("FOUND: " + hglddObject.obj_name)
138+
thisChildParentName.getOrElse("root")
139+
} else {
140+
println("NOT FOUND: " + s"tmpScope: $tmpScope" + s" hglddObject.obj_name ${hglddObject.obj_name}")
141+
tmpScope
142+
}
116143
}
117144
// Parse the kind of the object
118145
hglddObject.kind match {
119146
case s @ "struct" =>
120147
allElements.put(elId, (Name(obj_name, scope, parentModule), Direction("Unknown"), Type(s)))
121148
hglddObject.port_vars.foreach(parsePortVarFromModule(fileInfo, _, hglddObject.obj_name, parentModule))
122149
case "module" =>
150+
println("Module: " + hglddObject.obj_name + " " + scope + " " + parentModule + " " + elId)
123151
modules.put(elId, Name(obj_name, scope, parentModule))
124152
hglddObject.port_vars.foreach(parsePortVarFromModule(fileInfo, _, hglddObject.obj_name, hglddObject.obj_name))
125153
case a =>
@@ -167,7 +195,7 @@ class DebugIRParser(val workingDir: String, ddFilePath: String) {
167195
scope: String,
168196
parentModule: String,
169197
): Unit = {
170-
val elId = createId(fileInfo, portVar.hgl_loc, portVar.var_name)
198+
val elId = createId(fileInfo, portVar.hgl_loc, portVar.var_name + parentModule)
171199
val name = Name(portVar.var_name, scope, parentModule)
172200
val dir = Direction("Unknown")
173201
val typ = Type(portVar.type_name)

‎src/main/scala/tywaves/simulator/ParametricSimulatorInterface.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@ trait ParametricSimulatorInterface {
1010

1111
/** Use this method to run a simulations */
1212
def simulate[T <: RawModule](
13-
module: => T,
14-
settings: Seq[SimulatorSettings] = Seq(),
15-
simName: String = "defaultSimulation",
16-
)(body: T => Unit): Unit = {
13+
module: => T,
14+
settings: Seq[SimulatorSettings] = Seq(),
15+
simName: String = "defaultSimulation",
16+
)(body: T => Unit): Unit = {
1717
if (_resetSimulationBeforeRun)
1818
reset()
1919
simulator.simulate(module, settings, simName)(body)

‎src/main/scala/tywaves/simulator/SimulatorSettings.scala‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,6 @@ private[simulator] case class SaveWorkspace(name: String) extends SimulatorSetti
3737
*/
3838
private[simulator] case class FirtoolArgs(args: Seq[String]) extends SimulatorSettings
3939

40-
4140
/**
4241
* Package object to expose the simulator settings to the user. The following
4342
* settings can be used by a simulator to allow users to configure the

‎src/main/scala/tywaves/simulator/TywavesSimulator.scala‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,13 @@ object TywavesSimulator extends PeekPokeAPI {
2424
if (_resetSimulationBeforeRun)
2525
reset()
2626

27-
simulator.simulate(module, settings, simName)(body)
28-
2927
val containTywaves = settings.exists(_.isInstanceOf[Tywaves])
28+
29+
val finalSettings =
30+
if (containTywaves) settings ++ Seq(FirtoolArgs(Seq("-O=debug", "-g")))
31+
else settings
32+
simulator.simulate(module, finalSettings, simName)(body)
33+
3034
if (simulator.finalTracePath.nonEmpty && containTywaves) {
3135

3236
val mapChiselToVcd = new MapChiselToVcd(() => module, workingDir = simulator.wantedWorkspacePath)(
@@ -36,7 +40,7 @@ object TywavesSimulator extends PeekPokeAPI {
3640
)
3741
mapChiselToVcd.createTywavesState()
3842

39-
if (settings.contains(Tywaves(true)))
43+
if (finalSettings.contains(Tywaves(true)))
4044
TywavesInterface.run(simulator.finalTracePath.get, Some(mapChiselToVcd.tywavesStatePath))
4145

4246
} else if (containTywaves)

‎src/test/scala/hierarchicalmodules/MultiBlink.scala‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,16 +22,21 @@ class AnotherModule extends Module {
2222
}
2323
class AMultiBlink extends Module {
2424
val io = IO(new Bundle {
25-
val enable = Input(Bool())
26-
val leds = Output(UInt(4.W))
25+
val enable: Bool = Input(Bool())
26+
val leds: UInt = Output(UInt(4.W))
2727
})
2828

29-
val anotherModule = Module(new AnotherModule)
29+
val anotherModule: AnotherModule = Module(new AnotherModule)
30+
31+
val blinker: SubBlink = Module(new SubBlink(5))
32+
val blinker2: Blink = Module(new Blink(3))
3033

31-
val blinker = Module(new SubBlink(5))
3234
blinker.iox.enablex := io.enable
33-
when (anotherModule.out === 1.U) {
35+
blinker2.io.enable := io.enable
36+
37+
when(anotherModule.out === 1.U) {
3438
blinker.iox.enablex := false.B
39+
blinker2.io.enable := false.B
3540
}
3641
io.leds :=
3742
(blinker.iox.ledx << 3).asUInt + (blinker.iox.ledx << 2).asUInt + (blinker.iox.ledx << 1).asUInt + (blinker.iox.ledx << 0).asUInt

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