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| 1 | +//> using scala "2.13.14" |
| 2 | +//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT" |
| 3 | +//> using dep "org.chipsalliance::chisel:6.4.0" |
| 4 | +//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0" |
| 5 | +//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations" |
| 6 | +//> using dep "org.scalatest::scalatest:3.2.18" |
| 7 | + |
| 8 | +// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions) |
| 9 | +import tywaves.simulator._ |
| 10 | +import tywaves.simulator.simulatorSettings._ |
| 11 | +import chisel3._ |
| 12 | +// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._ |
| 13 | +//import _root_.circt.stage.ChiselStage |
| 14 | +import org.scalatest.funspec.AnyFunSpec |
| 15 | +import org.scalatest.matchers.should.Matchers |
| 16 | +import circt.stage.ChiselStage |
| 17 | + |
| 18 | +// Enum of possible states |
| 19 | +object MyFSMStates extends ChiselEnum { |
| 20 | + val IDLE, StateA, StateB, END = Value |
| 21 | +} |
| 22 | + |
| 23 | +class FSM extends Bundle { |
| 24 | + |
| 25 | + val inputState = IO(Input(MyFSMStates())) |
| 26 | + val state = RegInit(MyFSMStates.IDLE) |
| 27 | + val stateNxt = WireInit(MyFSMStates.IDLE) |
| 28 | + |
| 29 | + val endConst = WireInit(MyFSMStates.END) |
| 30 | + |
| 31 | + when(state === MyFSMStates.IDLE) { |
| 32 | + stateNxt := MyFSMStates.StateA |
| 33 | + }.elsewhen(state === MyFSMStates.StateA) { |
| 34 | + stateNxt := MyFSMStates.StateB |
| 35 | + }.elsewhen(state === MyFSMStates.StateB) { |
| 36 | + stateNxt := MyFSMStates.END |
| 37 | + }.otherwise { |
| 38 | + stateNxt := MyFSMStates.IDLE |
| 39 | + } |
| 40 | + |
| 41 | + when(inputState === MyFSMStates.END) { |
| 42 | + state := MyFSMStates.IDLE |
| 43 | + }.otherwise { |
| 44 | + state := stateNxt |
| 45 | + } |
| 46 | +} |
| 47 | + |
| 48 | +class MyFSM extends Module { |
| 49 | + val fsm = new FSM |
| 50 | + |
| 51 | + val io = IO(new Bundle { |
| 52 | + val inputState = Input(MyFSMStates()) |
| 53 | + }) |
| 54 | + |
| 55 | + val aConstBundle = Wire(new Bundle { |
| 56 | + val bit = Bool() |
| 57 | + val bv = UInt(32.W) |
| 58 | + val subbundle = new Bundle { |
| 59 | + val x = SInt(3.W) |
| 60 | + } |
| 61 | + }) |
| 62 | + aConstBundle.bit := 1.B |
| 63 | + aConstBundle.bv := 34.U |
| 64 | + aConstBundle.subbundle.x := 2.S |
| 65 | +} |
| 66 | + |
| 67 | + |
| 68 | +class MyFSMTest extends AnyFunSpec with Matchers { |
| 69 | + |
| 70 | + describe("TywavesSimulator") { |
| 71 | + it("runs MyFSM correctly") { |
| 72 | + import TywavesSimulator._ |
| 73 | + val chiselStage = new ChiselStage(true) |
| 74 | + |
| 75 | + chiselStage.execute( |
| 76 | + args = Array("--target", "chirrtl"), |
| 77 | + annotations = Seq( |
| 78 | + chisel3.stage.ChiselGeneratorAnnotation(() => new MyFSM()), |
| 79 | + circt.stage.FirtoolOption("-g"), |
| 80 | + circt.stage.FirtoolOption("--emit-hgldd"), |
| 81 | + ), |
| 82 | + ) |
| 83 | + simulate(new MyFSM(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = "runs_MYFSM_correctly_launch_tywaves") { |
| 84 | + fsm => |
| 85 | + fsm.clock.step(10) |
| 86 | + fsm.clock.step(10) |
| 87 | + } |
| 88 | + } |
| 89 | + } |
| 90 | + |
| 91 | +} |
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