Ensure that TywavesSimulator and TypedConverter uses the same firtool settings

Author: rameloni

example/Makefile

@@ -8,4 +8,5 @@ run: clean
 	done
 
 clean: 
-	$(RM) -rf test_run_dir/
+	$(RM) -rf test_run_dir/
+	$(RM) *.vcd *.fir

src/main/scala/tywaves/circuitmapper/TypedConverter.scala

@@ -14,20 +14,19 @@ private[tywaves] object TypedConverter {
   private val chiselStageBaseArgs =
     Array("--target", "systemverilog", "--split-verilog", "--firtool-binary-path", firtoolBinaryPath)
 
+  val firtoolBaseArgs: Seq[String] =
+    Seq("-O=debug", "-g", "--emit-hgldd", "--split-verilog") // Run in debug mode compiled with optimizations
   // Directories where the debug information is stored
   private var hglddDebugDir   = "hgldd/debug"
   private var hglddWithOptDir = "hgldd/opt" // TODO: remove
   private var workingDir: Option[String] = None
   private val topModuleName = TopModuleName(None)
 
   // Default firtool options encoded as annotations for ChiselStage
-  private val defaultFirtoolOptAnno =
-    createFirtoolOptions(Seq(
-      "--emit-hgldd"
-      //      "-disable-annotation-unknown",
-      //      "--hgldd-output-prefix=<path>",
-      /*,"--output-final-mlir=WORK.mlir"*/
-    ))
+  private val defaultFirtoolOptAnno = createFirtoolOptions(firtoolBaseArgs)
+  //      "-disable-annotation-unknown",
+  //      "--hgldd-output-prefix=<path>",
+  /*,"--output-final-mlir=WORK.mlir"*/
 
   // Map any sequence of string into FirtoolOptions
   private def createFirtoolOptions(args: Seq[String]) = args.map(circt.stage.FirtoolOption)
@@ -37,8 +36,9 @@ private[tywaves] object TypedConverter {
    * [[circt.stage.ChiselStage]]
    */
   def createDebugInfoHgldd[T <: RawModule](
-      generateModule: () => T,
-      workingDir:     String = "workingDir",
+      generateModule:        () => T,
+      workingDir:            String = "workingDir",
+      additionalFirtoolArgs: Seq[String],
   ): Unit = {
     this.workingDir = Some(workingDir)
     hglddWithOptDir = workingDir + "/" + hglddWithOptDir
@@ -54,10 +54,9 @@ private[tywaves] object TypedConverter {
     //      annotations,
     //    ) // execute returns the passThrough annotations in CIRCT transform stage
 
-    // Run with debug mode
     val finalAnno = chiselStage.execute(
       chiselStageBaseArgs ++ Array("--target-dir", hglddDebugDir),
-      annotations ++ createFirtoolOptions(Seq("-O=debug", "-g")),
+      createFirtoolOptions(additionalFirtoolArgs) ++ annotations ,
     ) // execute returns the passThrough annotations in CIRCT transform stage
 
     // Get the module name

src/main/scala/tywaves/simulator/ParametricSimulator.scala

@@ -60,6 +60,7 @@ class ParametricSimulator {
     else None
 
   private var _firtoolArgs: Seq[String] = Seq()
+  def getFirtoolArgs:       Seq[String] = _firtoolArgs
 
   /** Launch and execute a simulation given a list of [[SimulatorSettings]]. */
   def simulate[T <: RawModule](

src/main/scala/tywaves/simulator/TywavesSimulator.scala

@@ -31,7 +31,8 @@ object TywavesSimulator extends PeekPokeAPI {
 
     val finalSettings =
       if (containTywaves)
-        settings ++ Seq(FirtoolArgs(Seq("-O=debug", "-g", "--emit-hgldd", "--split-verilog", "-o=WORK.v")))
+        settings ++ Seq(FirtoolArgs(TypedConverter.firtoolBaseArgs))
+      // Seq(FirtoolArgs(Seq("-O=debug", "-g", "--emit-hgldd", "--split-verilog", "-o=WORK.v")))
       else settings
 
     simulator.simulate(module, finalSettings, simName)(body)
@@ -43,7 +44,11 @@ object TywavesSimulator extends PeekPokeAPI {
       // Create the debug info from the firtool and get the top module name
       // TODO: this may not be needed anymore, since the debug info can be generated directly from chiselsim, by giving the right options to firtool
       // But the problem is to call chiselstage with debug options
-      TypedConverter.createDebugInfoHgldd(() => module, simulator.wantedWorkspacePath)
+      TypedConverter.createDebugInfoHgldd(
+        () => module,
+        workingDir = simulator.wantedWorkspacePath,
+        additionalFirtoolArgs = simulator.getFirtoolArgs,
+      )
 
       // Run tywaves viewer if the Tywaves waveform generation is enabled by Tywaves(true)
       val (runWaves, waitFor) =