Mailboxes

Draft

This page is a stub for completion by someone who knows more than I about the subject.

Overview

Mailboxes facilitate communication between the ARM and the VideoCore. This page lists the available mailboxes/channels.

Mailbox registers

The following table shows the register offsets for the different mailboxes. For a description of the procedure for using these registers to access a mailbox, see [here](Accessing mailboxes).

Mailbox Peek  Read  Write  Status  Sender  Config
   0    0x10  0x00  0x20   0x18    0x14    0x1C
   1    0x20

Channels

The following lists the currently defined mailbox channels, with links to pages describing the format of the messages.

Mailbox 0 defines the following channels:

0: Framebuffer access
1:
2:
3:
4:
5:
6:
7:
8: [Property tag request (ARM -> VC)](Mailbox property interface)
9: Property tag request (VC -> ARM)