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tq-steina
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media: i2c: imx415: Add more clock configurations
Commit b814b5b upstream. Complete the list from "INCK Setting" section in IMX415-AAQR-C (Rev. E19504, 2019/05/21). For consistency suffix all lane rate values by UL, which is needed for 2376000000 anyway. Signed-off-by: Alexander Stein <[email protected]> Signed-off-by: Sakari Ailus <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
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‎drivers/media/i2c/imx415.c

Lines changed: 260 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ struct imx415_clk_params {
124124
/* INCK Settings - includes all lane rate and INCK dependent registers */
125125
static const struct imx415_clk_params imx415_clk_params[] = {
126126
{
127-
.lane_rate = 594000000,
127+
.lane_rate = 594000000UL,
128128
.inck = 27000000,
129129
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
130130
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
@@ -139,7 +139,37 @@ static const struct imx415_clk_params imx415_clk_params[] = {
139139
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
140140
},
141141
{
142-
.lane_rate = 720000000,
142+
.lane_rate = 594000000UL,
143+
.inck = 37125000,
144+
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
145+
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
146+
.regs[2] = { IMX415_SYS_MODE, 0x7 },
147+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
148+
.regs[4] = { IMX415_INCKSEL2, 0x24 },
149+
.regs[5] = { IMX415_INCKSEL3, 0x080 },
150+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
151+
.regs[7] = { IMX415_INCKSEL5, 0x24 },
152+
.regs[8] = { IMX415_INCKSEL6, 0x0 },
153+
.regs[9] = { IMX415_INCKSEL7, 0x1 },
154+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },
155+
},
156+
{
157+
.lane_rate = 594000000UL,
158+
.inck = 74250000,
159+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
160+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
161+
.regs[2] = { IMX415_SYS_MODE, 0x7 },
162+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
163+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
164+
.regs[5] = { IMX415_INCKSEL3, 0x080 },
165+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
166+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
167+
.regs[8] = { IMX415_INCKSEL6, 0x0 },
168+
.regs[9] = { IMX415_INCKSEL7, 0x1 },
169+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
170+
},
171+
{
172+
.lane_rate = 720000000UL,
143173
.inck = 24000000,
144174
.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
145175
.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
@@ -154,7 +184,22 @@ static const struct imx415_clk_params imx415_clk_params[] = {
154184
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
155185
},
156186
{
157-
.lane_rate = 891000000,
187+
.lane_rate = 720000000UL,
188+
.inck = 72000000,
189+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
190+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
191+
.regs[2] = { IMX415_SYS_MODE, 0x9 },
192+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
193+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
194+
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
195+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
196+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
197+
.regs[8] = { IMX415_INCKSEL6, 0x0 },
198+
.regs[9] = { IMX415_INCKSEL7, 0x1 },
199+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
200+
},
201+
{
202+
.lane_rate = 891000000UL,
158203
.inck = 27000000,
159204
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
160205
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
@@ -169,7 +214,37 @@ static const struct imx415_clk_params imx415_clk_params[] = {
169214
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
170215
},
171216
{
172-
.lane_rate = 1440000000,
217+
.lane_rate = 891000000UL,
218+
.inck = 37125000,
219+
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
220+
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
221+
.regs[2] = { IMX415_SYS_MODE, 0x5 },
222+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
223+
.regs[4] = { IMX415_INCKSEL2, 0x24 },
224+
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
225+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
226+
.regs[7] = { IMX415_INCKSEL5, 0x24 },
227+
.regs[8] = { IMX415_INCKSEL6, 0x0 },
228+
.regs[9] = { IMX415_INCKSEL7, 0x1 },
229+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
230+
},
231+
{
232+
.lane_rate = 891000000UL,
233+
.inck = 74250000,
234+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
235+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
236+
.regs[2] = { IMX415_SYS_MODE, 0x5 },
237+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
238+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
239+
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
240+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
241+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
242+
.regs[8] = { IMX415_INCKSEL6, 0x0 },
243+
.regs[9] = { IMX415_INCKSEL7, 0x1 },
244+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
245+
},
246+
{
247+
.lane_rate = 1440000000UL,
173248
.inck = 24000000,
174249
.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
175250
.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
@@ -184,7 +259,22 @@ static const struct imx415_clk_params imx415_clk_params[] = {
184259
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
185260
},
186261
{
187-
.lane_rate = 1485000000,
262+
.lane_rate = 1440000000UL,
263+
.inck = 72000000,
264+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
265+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
266+
.regs[2] = { IMX415_SYS_MODE, 0x8 },
267+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
268+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
269+
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
270+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
271+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
272+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
273+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
274+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
275+
},
276+
{
277+
.lane_rate = 1485000000UL,
188278
.inck = 27000000,
189279
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
190280
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
@@ -198,6 +288,171 @@ static const struct imx415_clk_params imx415_clk_params[] = {
198288
.regs[9] = { IMX415_INCKSEL7, 0x0 },
199289
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
200290
},
291+
{
292+
.lane_rate = 1485000000UL,
293+
.inck = 37125000,
294+
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
295+
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
296+
.regs[2] = { IMX415_SYS_MODE, 0x8 },
297+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
298+
.regs[4] = { IMX415_INCKSEL2, 0x24 },
299+
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
300+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
301+
.regs[7] = { IMX415_INCKSEL5, 0x24 },
302+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
303+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
304+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
305+
},
306+
{
307+
.lane_rate = 1485000000UL,
308+
.inck = 74250000,
309+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
310+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
311+
.regs[2] = { IMX415_SYS_MODE, 0x8 },
312+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
313+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
314+
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
315+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
316+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
317+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
318+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
319+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
320+
},
321+
{
322+
.lane_rate = 1782000000UL,
323+
.inck = 27000000,
324+
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
325+
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
326+
.regs[2] = { IMX415_SYS_MODE, 0x4 },
327+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
328+
.regs[4] = { IMX415_INCKSEL2, 0x23 },
329+
.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
330+
.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
331+
.regs[7] = { IMX415_INCKSEL5, 0x23 },
332+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
333+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
334+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
335+
},
336+
{
337+
.lane_rate = 1782000000UL,
338+
.inck = 37125000,
339+
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
340+
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
341+
.regs[2] = { IMX415_SYS_MODE, 0x4 },
342+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
343+
.regs[4] = { IMX415_INCKSEL2, 0x24 },
344+
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
345+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
346+
.regs[7] = { IMX415_INCKSEL5, 0x24 },
347+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
348+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
349+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
350+
},
351+
{
352+
.lane_rate = 1782000000UL,
353+
.inck = 74250000,
354+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
355+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
356+
.regs[2] = { IMX415_SYS_MODE, 0x4 },
357+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
358+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
359+
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
360+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
361+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
362+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
363+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
364+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
365+
},
366+
{
367+
.lane_rate = 2079000000UL,
368+
.inck = 27000000,
369+
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
370+
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
371+
.regs[2] = { IMX415_SYS_MODE, 0x2 },
372+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
373+
.regs[4] = { IMX415_INCKSEL2, 0x23 },
374+
.regs[5] = { IMX415_INCKSEL3, 0x0E7 },
375+
.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
376+
.regs[7] = { IMX415_INCKSEL5, 0x23 },
377+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
378+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
379+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
380+
},
381+
{
382+
.lane_rate = 2079000000UL,
383+
.inck = 37125000,
384+
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
385+
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
386+
.regs[2] = { IMX415_SYS_MODE, 0x2 },
387+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
388+
.regs[4] = { IMX415_INCKSEL2, 0x24 },
389+
.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
390+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
391+
.regs[7] = { IMX415_INCKSEL5, 0x24 },
392+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
393+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
394+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
395+
},
396+
{
397+
.lane_rate = 2079000000UL,
398+
.inck = 74250000,
399+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
400+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
401+
.regs[2] = { IMX415_SYS_MODE, 0x2 },
402+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
403+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
404+
.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
405+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
406+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
407+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
408+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
409+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
410+
},
411+
{
412+
.lane_rate = 2376000000UL,
413+
.inck = 27000000,
414+
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
415+
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
416+
.regs[2] = { IMX415_SYS_MODE, 0x0 },
417+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
418+
.regs[4] = { IMX415_INCKSEL2, 0x23 },
419+
.regs[5] = { IMX415_INCKSEL3, 0x108 },
420+
.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
421+
.regs[7] = { IMX415_INCKSEL5, 0x23 },
422+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
423+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
424+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
425+
},
426+
{
427+
.lane_rate = 2376000000UL,
428+
.inck = 37125000,
429+
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
430+
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
431+
.regs[2] = { IMX415_SYS_MODE, 0x0 },
432+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
433+
.regs[4] = { IMX415_INCKSEL2, 0x24 },
434+
.regs[5] = { IMX415_INCKSEL3, 0x100 },
435+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
436+
.regs[7] = { IMX415_INCKSEL5, 0x24 },
437+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
438+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
439+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
440+
},
441+
{
442+
.lane_rate = 2376000000UL,
443+
.inck = 74250000,
444+
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
445+
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
446+
.regs[2] = { IMX415_SYS_MODE, 0x0 },
447+
.regs[3] = { IMX415_INCKSEL1, 0x00 },
448+
.regs[4] = { IMX415_INCKSEL2, 0x28 },
449+
.regs[5] = { IMX415_INCKSEL3, 0x100 },
450+
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
451+
.regs[7] = { IMX415_INCKSEL5, 0x28 },
452+
.regs[8] = { IMX415_INCKSEL6, 0x1 },
453+
.regs[9] = { IMX415_INCKSEL7, 0x0 },
454+
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
455+
},
201456
};
202457

203458
/* all-pixel 2-lane 720 Mbps 15.74 Hz mode */

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