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Merge remote-tracking branch 'stable/linux-6.12.y' into rpi-6.12.y
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‎Documentation/bpf/bpf_devel_QA.rst

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@@ -382,6 +382,14 @@ In case of new BPF instructions, once the changes have been accepted
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into the Linux kernel, please implement support into LLVM's BPF back
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end. See LLVM_ section below for further information.
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Q: What "BPF_INTERNAL" symbol namespace is for?
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-----------------------------------------------
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A: Symbols exported as BPF_INTERNAL can only be used by BPF infrastructure
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like preload kernel modules with light skeleton. Most symbols outside
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of BPF_INTERNAL are not expected to be used by code outside of BPF either.
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Symbols may lack the designation because they predate the namespaces,
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or due to an oversight.
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Stable submission
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=================
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‎Makefile

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# SPDX-License-Identifier: GPL-2.0
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VERSION = 6
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PATCHLEVEL = 12
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SUBLEVEL = 25
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SUBLEVEL = 27
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EXTRAVERSION =
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NAME = Baby Opossum Posse
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‎arch/arm/crypto/Kconfig

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menu "Accelerated Cryptographic Algorithms for CPU (arm)"
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config CRYPTO_CURVE25519_NEON
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tristate "Public key crypto: Curve25519 (NEON)"
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tristate
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depends on KERNEL_MODE_NEON
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select CRYPTO_KPP
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select CRYPTO_LIB_CURVE25519_GENERIC
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select CRYPTO_ARCH_HAVE_LIB_CURVE25519
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default CRYPTO_LIB_CURVE25519_INTERNAL
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help
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Curve25519 algorithm
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- NEON (Advanced SIMD) extensions
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config CRYPTO_POLY1305_ARM
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tristate "Hash functions: Poly1305 (NEON)"
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tristate
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select CRYPTO_HASH
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select CRYPTO_ARCH_HAVE_LIB_POLY1305
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default CRYPTO_LIB_POLY1305_INTERNAL
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help
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Poly1305 authenticator algorithm (RFC7539)
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- ARMv8 Crypto Extensions
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config CRYPTO_CHACHA20_NEON
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tristate "Ciphers: ChaCha20, XChaCha20, XChaCha12 (NEON)"
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tristate
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select CRYPTO_SKCIPHER
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select CRYPTO_ARCH_HAVE_LIB_CHACHA
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default CRYPTO_LIB_CHACHA_INTERNAL
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help
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Length-preserving ciphers: ChaCha20, XChaCha20, and XChaCha12
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stream cipher algorithms

‎arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for J784S4 and J742S2 SoC Family
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*
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* TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
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* TRM (j742s2): https://www.ti.com/lit/pdf/spruje3
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*
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* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/ {
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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L2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a72_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a72-pmu";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@100000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
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<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
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<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
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<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
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<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
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<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
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<0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
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<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
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<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
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<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
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<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
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<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
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<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
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<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
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<0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
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<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
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<0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
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<0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
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<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
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<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
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<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
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/* MCUSS_WKUP Range */
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
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<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
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cbass_mcu_wakeup: bus@28380000 {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
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<0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
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};
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};
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thermal_zones: thermal-zones {
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#include "k3-j784s4-j742s2-thermal-common.dtsi"
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};
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};
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/* Now include peripherals from each bus segment */
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#include "k3-j784s4-j742s2-main-common.dtsi"
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#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi"

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