clk: rp1: Allow audio out to use PLL_AUDIO_SEC; workaround rounding error

Connect PLL_AUDIO_SEC to CLK_AUDIO_OUT, which had been commented out
to avoid interference with I2S: we expect them never to be enabled
at the same time. Work around a rounding error that occurs when the
desired rate is exactly the max but not exactly achievable by the PLL.

Signed-off-by: Nick Hollinghurst <[email protected]>

Author: njhollinghurst

drivers/clk/clk-rp1.c

@@ -1083,9 +1083,11 @@ static void rp1_clock_choose_div_and_prate(struct clk_hw *hw,
 	/*
 	 * Prevent overclocks - if all parent choices result in
 	 * a downstream clock in excess of the maximum, then the
-	 * call to set the clock will fail.
+	 * call to set the clock will fail. But due to round-to-
+	 * nearest in the PLL core (which has 24 fractional bits),
+	 * it's expedient to tolerate a tiny error (1Hz/33MHz).
 	 */
-	if (tmp > data->max_freq)
+	if (tmp > data->max_freq + (data->max_freq >> 25))
 		*calc_rate = 0;
 	else
 		*calc_rate = tmp;
@@ -1738,7 +1740,7 @@ static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_audio_out_parents[] = {
 	{ .index = -1 },
-	{ .index = -1 },
+	{ .hw = &pll_audio_sec_desc.hw },
 	{ .hw = &pll_video_sec_desc.hw },
 	{ .index = 0 },
 };