drivers: media: cfe: Add non-continuous CSI-2 clock mode

Set the DPHY block to manual clock lane termination enable and HS mode
i V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK is absent in the bus flags.

Signed-off-by: Naushir Patuck <[email protected]>

Author: naushir

drivers/media/platform/raspberrypi/rp1_cfe/cfe.c

@@ -1166,6 +1166,9 @@ static int cfe_start_streaming(struct vb2_queue *vq, unsigned int count)
 		goto err_disable_cfe;
 	}
 
+	cfe->csi2.dphy.noncontinuous_clock = mbus_config.bus.mipi_csi2.flags &
+					     V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
+
 	cfe_dbg("Configuring CSI-2 block - %u data lanes\n", cfe->csi2.dphy.active_lanes);
 	cfe->csi2.dphy.dphy_rate = sensor_link_rate(cfe) / 1000000UL;
 	csi2_open_rx(&cfe->csi2);

drivers/media/platform/raspberrypi/rp1_cfe/dphy.c

@@ -30,6 +30,7 @@
 #define PHY2_TST_CTRL1	0x05c
 
 /* DW dphy Host Transactions */
+#define DPHY_HS_RX_CTRL_CLK_OFFSET	0x34
 #define DPHY_HS_RX_CTRL_LANE0_OFFSET	0x44
 #define DPHY_PLL_INPUT_DIV_OFFSET	0x17
 #define DPHY_PLL_LOOP_DIV_OFFSET	0x18
@@ -128,6 +129,20 @@ static void dphy_set_hsfreqrange(struct dphy_data *dphy, uint32_t mbps)
 			 hsfreqrange_table[i][1] << 1);
 }
 
+static void dphy_set_manual_clock_term(struct dphy_data *dphy)
+{
+	/* See page 162 of the dphy databook */
+	const u8 tst = (1 << 0) + /* HS RX power on */
+		       (1 << 1) + /* Bypass HS RX power on */
+		       (1 << 2) + /* HS RX cal enable */
+		       (0 << 3) + /* HS RX cal control */
+		       (1 << 4) + /* Term EN */
+		       (1 << 5) + /* Term EN control */
+		       (2 << 6);  /* Set 0 */
+
+	dphy_transaction(dphy, DPHY_HS_RX_CTRL_CLK_OFFSET, tst);
+}
+
 static void dphy_init(struct dphy_data *dphy)
 {
 	dw_csi2_host_write(dphy, PHY_RSTZ, 0);
@@ -141,6 +156,9 @@ static void dphy_init(struct dphy_data *dphy)
 
 	dphy_set_hsfreqrange(dphy, dphy->dphy_rate);
 
+	if (!dphy->noncontinuous_clock)
+		dphy_set_manual_clock_term(dphy);
+
 	usleep_range(5, 10);
 	dw_csi2_host_write(dphy, PHY_SHUTDOWNZ, 1);
 	usleep_range(5, 10);

drivers/media/platform/raspberrypi/rp1_cfe/dphy.h

@@ -18,6 +18,7 @@ struct dphy_data {
 	u32 dphy_rate;
 	u32 max_lanes;
 	u32 active_lanes;
+	bool noncontinuous_clock;
 };
 
 void dphy_probe(struct dphy_data *dphy);