drivers: dwc_otg: add ticket-based spinlock for ARM64

The ARM64 architecture uses qspinlock which has a fast and slow path.
This isn't ideal for all claimers of a lock operating in interrupt
context. Add a ticket-based lock similar to the armv6/7 implementation.

Based on an upstream patch that was abandoned in favour of qspinlock.

Link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/

Signed-off-by: Jonathan Bell <[email protected]>

Author: P33M

drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h

@@ -129,12 +129,6 @@ enum fiq_debug_level {
 	FIQDBG_PORTHUB = (1 << 3),
 };
 
-#ifdef CONFIG_ARM64
-
-typedef spinlock_t fiq_lock_t;
-
-#else
-
 #define TICKET_SHIFT 16
 typedef struct {
 	union {
@@ -146,18 +140,45 @@ typedef struct {
 	};
 } __aligned(4) fiq_lock_t;
 
-#endif
-
-#ifdef CONFIG_ARM64
-
+#if defined(CONFIG_ARM64)
 static inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
 {
-	spin_lock((spinlock_t *)lock);
+	unsigned int tmp;
+	fiq_lock_t lockval, newval;
+
+	asm volatile(
+	/* Atomically increment the next ticket. */
+	"	prfm	pstl1strm, %3\n"
+	"1:	ldaxr	%w0, %3\n"
+	"	add	%w1, %w0, %w5\n"
+	"	stxr	%w2, %w1, %3\n"
+	"	cbnz	%w2, 1b\n"
+	/* Did we get the lock? */
+	"	eor	%w1, %w0, %w0, ror #16\n"
+	"	cbz	%w1, 3f\n"
+	/*
+	 * No: spin on the owner. Send a local event to avoid missing an
+	 * unlock before the exclusive load.
+	 */
+	"	sevl\n"
+	"2:	wfe\n"
+	"	ldaxrh	%w2, %4\n"
+	"	eor	%w1, %w2, %w0, lsr #16\n"
+	"	cbnz	%w1, 2b\n"
+	/* We got the lock. Critical section starts here. */
+	"3:"
+	: "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)
+	: "Q" (lock->tickets.owner), "I" (1 << TICKET_SHIFT)
+	: "memory");
 }
 
 static inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
 {
-	spin_unlock((spinlock_t *)lock);
+	asm volatile(
+	"	stlrh	%w1, %0\n"
+	: "=Q" (lock->tickets.owner)
+	: "r" (lock->tickets.owner + 1)
+	: "memory");
 }
 
 #else

drivers/usb/host/dwc_otg/dwc_otg_hcd.c

@@ -1044,10 +1044,6 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
 		}
 		DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
 
-#ifdef CONFIG_ARM64
-		spin_lock_init(&hcd->fiq_state->lock);
-#endif
-
 		hcd->fiq_state->dummy_send = DWC_DMA_ALLOC_ATOMIC(dev, 16,
 							 &hcd->fiq_state->dummy_send_dma);