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7 | 7 | #define _HAILO_IOCTL_COMMON_H_ |
8 | 8 |
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9 | 9 | #define HAILO_DRV_VER_MAJOR 4 |
10 | | -#define HAILO_DRV_VER_MINOR 19 |
| 10 | +#define HAILO_DRV_VER_MINOR 20 |
11 | 11 | #define HAILO_DRV_VER_REVISION 0 |
12 | 12 |
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13 | 13 | #define _STRINGIFY_EXPANDED( x ) #x |
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22 | 22 | #define MAX_VDMA_ENGINES (3) |
23 | 23 | #define SIZE_OF_VDMA_DESCRIPTOR (16) |
24 | 24 | #define VDMA_DEST_CHANNELS_START (16) |
| 25 | +#define MAX_SG_DESCS_COUNT (64 * 1024u) |
25 | 26 |
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26 | 27 | #define HAILO_VDMA_MAX_ONGOING_TRANSFERS (128) |
27 | 28 | #define HAILO_VDMA_MAX_ONGOING_TRANSFERS_MASK (HAILO_VDMA_MAX_ONGOING_TRANSFERS - 1) |
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38 | 39 | #define FW_ACCESS_APP_CPU_CONTROL_MASK (1 << FW_ACCESS_CONTROL_INTERRUPT_SHIFT) |
39 | 40 | #define FW_ACCESS_DRIVER_SHUTDOWN_SHIFT (2) |
40 | 41 | #define FW_ACCESS_DRIVER_SHUTDOWN_MASK (1 << FW_ACCESS_DRIVER_SHUTDOWN_SHIFT) |
| 42 | +// HRT-15790 TODO: separate nnc interrupts and soc interrupts |
| 43 | +#define FW_ACCESS_SOFT_RESET_SHIFT (3) |
| 44 | +#define FW_ACCESS_SOFT_RESET_MASK (1 << FW_ACCESS_SOFT_RESET_SHIFT) |
| 45 | + |
41 | 46 | #define FW_ACCESS_SOC_CONTROL_SHIFT (3) |
42 | 47 | #define FW_ACCESS_SOC_CONTROL_MASK (1 << FW_ACCESS_SOC_CONTROL_SHIFT) |
43 | 48 |
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@@ -184,7 +189,6 @@ enum hailo_dma_data_direction { |
184 | 189 | }; |
185 | 190 |
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186 | 191 | // Enum that states what type of buffer we are working with in the driver |
187 | | -// TODO: HRT-13580 - Add specific type for user allocated and for driver allocated |
188 | 192 | enum hailo_dma_buffer_type { |
189 | 193 | HAILO_DMA_USER_PTR_BUFFER = 0, |
190 | 194 | HAILO_DMA_DMABUF_BUFFER = 1, |
@@ -399,7 +403,7 @@ struct hailo_d2h_notification { |
399 | 403 | enum hailo_board_type { |
400 | 404 | HAILO_BOARD_TYPE_HAILO8 = 0, |
401 | 405 | HAILO_BOARD_TYPE_HAILO15, |
402 | | - HAILO_BOARD_TYPE_PLUTO, |
| 406 | + HAILO_BOARD_TYPE_HAILO15L, |
403 | 407 | HAILO_BOARD_TYPE_HAILO10H, |
404 | 408 | HAILO_BOARD_TYPE_HAILO10H_LEGACY, |
405 | 409 | HAILO_BOARD_TYPE_COUNT, |
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