fix up again to support max dividers

Author: kilograham

src/rp2_common/hardware_clocks/clocks.c

@@ -101,14 +101,22 @@ bool clock_configure(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32
     if (freq > src_freq)
         return false;
 
-    uint32_t div = (uint32_t)((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / freq);
+    uint64_t div64 =((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / freq);
+    uint32_t div, actual_freq;
+    if (div64 >> 32) {
+        // set div to 0 for maximum clock divider
+        div = 0;
+        actual_freq = src_freq >> (32 - CLOCKS_CLK_GPOUT0_DIV_INT_LSB);
+    } else {
+        div = div64;
 #if PICO_RP2040
-    // on RP2040 only clock divider of 1, or  >= 2 are supported
-    if (div < (2u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB)) {
-        div = (1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB);
-    }
+        // on RP2040 only clock divider of 1, or  >= 2 are supported
+        if (div < (2u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB)) {
+            div = (1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB);
+        }
 #endif
-    uint32_t actual_freq = (uint32_t) ((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / div);
+        actual_freq = (uint32_t) ((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / div);
+    }
 
     clock_configure_internal(clock, src, auxsrc, actual_freq, div);
     // Store the configured frequency

src/rp2_common/hardware_clocks/include/hardware/clocks.h

@@ -270,11 +270,11 @@ typedef clock_num_t clock_handle_t;
  * achievable, with the maximum being the src_freq.
  *
  * \if rp2350_specific
- * Note: That the RP2350 clock hardware supports divisors from 1.0->65535.0 in steps of 1/65536
+ * Note: The RP2350 clock hardware supports divisors from 1.0->65536.0 in steps of 1/65536
  *
  * \endif
  * \if rp2030_specific
- * Note: That the RP2040 clock hardware only support divisors of exactly 1.0 or 2.0->65535.0 in steps of 1/256
+ * Note: The RP2040 clock hardware only supports divisors of exactly 1.0 or 2.0->16777216.0 in steps of 1/256
  * \endif
  *
  * See the tables in the description for details on the possible values for clock sources.