Small API additions and minor fixes (#406)

* Add missing DREQ_s

* store actual clock frequency in clock_configure (fixes #368)

* use dma DREQ values defined in dreqs/dma.h

* Fix hw_is_claimed, and add xxx_is_claimed APIs

* Add some PIO irq helper methods

* Add DMA channel IRQ status getter and clear methods

* Implement the correct PIO IRQ status/clear methods (good to have methods here as the h/w interrupt registers are super confusing)

* fix pico_multicore dependencies

* add missing wrapper func __aeabi_f2d

* Further DMA/PIO IRQ API cleanup (and review fixes)

* add PICO_INT64_OPS_IN_RAM flag

Author: kilograham

cmake/preload/toolchains/pico_arm_gcc.cmake

@@ -12,7 +12,7 @@ if (NOT PICO_GCC_TRIPLE)
         message("PICO_GCC_TRIPLE set from environment: $ENV{PICO_GCC_TRIPLE}")
     else()
         set(PICO_GCC_TRIPLE arm-none-eabi)
-        pico_message_debug("PICO_GCC_TRIPLE defaulted to arm-none-eabi")
+        #pico_message_debug("PICO_GCC_TRIPLE defaulted to arm-none-eabi")
     endif()
 endif()
 

src/common/pico_time/time.c

@@ -283,7 +283,7 @@ static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
 #endif
 }
 
-static int64_t repeating_timer_callback(__unused alarm_id_t id, __unused void *user_data) {
+static int64_t repeating_timer_callback(__unused alarm_id_t id, void *user_data) {
     repeating_timer_t *rt = (repeating_timer_t *)user_data;
     assert(rt->alarm_id == id);
     if (rt->callback(rt)) {

src/rp2_common/cmsis/CMakeLists.txt

@@ -50,7 +50,7 @@ set(PICO_CMSIS_VENDOR RaspberryPi)
 set(PICO_CMSIS_DEVICE RP2040)
 
 if (PICO_CMSIS_CORE_PATH)
-    add_library(cmsis_core INTERFACE)
+    pico_add_impl_library(cmsis_core)
     target_sources(cmsis_core INTERFACE
             ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Source/system_${PICO_CMSIS_DEVICE}.c
     )

src/rp2_common/cmsis/include/cmsis/rename_exceptions.h

@@ -7,6 +7,7 @@
 #ifndef _CMSIS_RENAME_EXCEPTIONS_H
 #define _CMSIS_RENAME_EXCEPTIONS_H
 
+#if LIB_CMSIS_CORE
 // PICO_CONFIG: PICO_CMSIS_RENAME_EXCEPTIONS, Whether to rename SDK exceptions such as isr_nmi to their CMSIS equivalent i.e. NMI_Handler, type=bool, default=1, group=cmsis_core
 
 // Note that since this header is included at the config stage, if you wish to override this you should do so via build compiler define
@@ -48,4 +49,5 @@
 #define isr_irq25 RTC_IRQ_Handler
 #endif
 
+#endif
 #endif /* _CMSIS_RENAME_EXCEPTIONS_H */

src/rp2_common/hardware_claim/claim.c

@@ -14,22 +14,13 @@ void hw_claim_unlock(uint32_t save) {
     spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save);
 }
 
-bool hw_is_claimed(uint8_t *bits, uint bit_index) {
-    bool rc;
-    uint32_t save = hw_claim_lock();
-    if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) {
-        rc = false;
-    } else {
-        bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
-        rc = true;
-    }
-    hw_claim_unlock(save);
-    return rc;
+inline bool hw_is_claimed(const uint8_t *bits, uint bit_index) {
+    return (bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
 }
 
 void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) {
     uint32_t save = hw_claim_lock();
-    if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) {
+    if (hw_is_claimed(bits, bit_index)) {
         panic(message, bit_index);
     } else {
         bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
@@ -42,7 +33,7 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint
     uint32_t save = hw_claim_lock();
     int found_bit = -1;
     for(uint bit=bit_lsb; bit <= bit_msb; bit++) {
-        if (!(bits[bit >> 3u] & (1u << (bit & 7u)))) {
+        if (!hw_is_claimed(bits, bit)) {
             bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u));
             found_bit = (int)bit;
             break;
@@ -57,7 +48,7 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint
 
 void hw_claim_clear(uint8_t *bits, uint bit_index) {
     uint32_t save = hw_claim_lock();
-    assert(bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
+    assert(hw_is_claimed(bits, bit_index));
     bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u));
     hw_claim_unlock(save);
 }

src/rp2_common/hardware_claim/include/hardware/claim.h

@@ -65,10 +65,10 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint
  * The resource ownership is indicated by the bit_index bit in an array of bits.
  *
  * \param bits pointer to an array of bits (8 bits per byte)
- * \param bit_index resource to unclaim (bit index into array of bits)
+ * \param bit_index resource to check (bit index into array of bits)
  * \return true if the resource is claimed
  */
-bool hw_is_claimed(uint8_t *bits, uint bit_index);
+bool hw_is_claimed(const uint8_t *bits, uint bit_index);
 
 /*! \brief Atomically unclaim a resource
  *  \ingroup hardware_claim

src/rp2_common/hardware_clocks/clocks.c

@@ -112,7 +112,7 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc,
     clock->div = div;
 
     // Store the configured frequency
-    configured_freq[clk_index] = freq;
+    configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div);
 
     return true;
 }

src/rp2_common/hardware_dma/dma.c

@@ -39,6 +39,11 @@ int dma_claim_unused_channel(bool required) {
     return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available");
 }
 
+bool dma_channel_is_claimed(uint channel) {
+    check_dma_channel_param(channel);
+    return hw_is_claimed((uint8_t *) &_claimed, channel);
+}
+
 #ifndef NDEBUG
 
 void print_dma_ctrl(dma_channel_hw_t *channel) {

src/rp2_common/hardware_dma/include/hardware/dma.h

@@ -34,8 +34,12 @@ extern "C" {
  * * Memory to memory
  */
 
-// this is not defined in generated dreq.h
-#define DREQ_FORCE  63
+// these are not defined in generated dreq.h
+#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0
+#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1
+#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2
+#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3
+#define DREQ_FORCE      DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT
 
 // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma
 #ifndef PARAM_ASSERTIONS_ENABLED_DMA
@@ -94,6 +98,16 @@ void dma_channel_unclaim(uint channel);
  */
 int dma_claim_unused_channel(bool required);
 
+/*! \brief Determine if a dma channel is claimed
+ *  \ingroup hardware_dma
+ *
+ * \param channel the dma channel
+ * \return true if the channel is claimed, false otherwise
+ * \see dma_channel_claim
+ * \see dma_channel_claim_mask
+ */
+bool dma_channel_is_claimed(uint channel);
+
 /** \brief DMA channel configuration
  *  \defgroup channel_config channel_config
  *  \ingroup hardware_dma
@@ -465,7 +479,7 @@ static inline void dma_channel_abort(uint channel) {
     while (dma_hw->abort & (1ul << channel)) tight_loop_contents();
 }
 
-/*! \brief  Enable single DMA channel interrupt 0
+/*! \brief  Enable single DMA channel's interrupt via DMA_IRQ_0
  *  \ingroup hardware_dma
  *
  * \param channel DMA channel
@@ -480,7 +494,7 @@ static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) {
         hw_clear_bits(&dma_hw->inte0, 1u << channel);
 }
 
-/*! \brief  Enable multiple DMA channels interrupt 0
+/*! \brief  Enable multiple DMA channels' interrupts via DMA_IRQ_0
  *  \ingroup hardware_dma
  *
  * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
@@ -494,7 +508,7 @@ static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool
     }
 }
 
-/*! \brief  Enable single DMA channel interrupt 1
+/*! \brief  Enable single DMA channel's interrupt via DMA_IRQ_1
  *  \ingroup hardware_dma
  *
  * \param channel DMA channel
@@ -509,7 +523,7 @@ static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) {
         hw_clear_bits(&dma_hw->inte1, 1u << channel);
 }
 
-/*! \brief  Enable multiple DMA channels interrupt 0
+/*! \brief  Enable multiple DMA channels' interrupts via DMA_IRQ_1
  *  \ingroup hardware_dma
  *
  * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
@@ -523,6 +537,105 @@ static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool
     }
 }
 
+/*! \brief  Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt via irq_index for specified channel, false to disable.
+ */
+static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) {
+    invalid_params_if(DMA, irq_index > 1);
+    if (irq_index) {
+        dma_channel_set_irq1_enabled(channel, enabled);
+    } else {
+        dma_channel_set_irq0_enabled(channel, enabled);
+    }
+}
+
+/*! \brief  Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask,  bool enabled) {
+    invalid_params_if(DMA, irq_index > 1);
+    if (irq_index) {
+        dma_set_irq1_channel_mask_enabled(channel_mask, enabled);
+    } else {
+        dma_set_irq0_channel_mask_enabled(channel_mask, enabled);
+    }
+}
+
+/*! \brief  Determine if a particular channel is a cause of DMA_IRQ_0
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_0, false otherwise
+ */
+static inline bool dma_channel_get_irq0_status(uint channel) {
+    check_dma_channel_param(channel);
+    return dma_hw->ints0 & (1u << channel);
+}
+
+/*! \brief  Determine if a particular channel is a cause of DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_1, false otherwise
+ */
+static inline bool dma_channel_get_irq1_status(uint channel) {
+    check_dma_channel_param(channel);
+    return dma_hw->ints1 & (1u << channel);
+}
+
+/*! \brief  Determine if a particular channel is a cause of DMA_IRQ_N
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise
+ */
+static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
+    invalid_params_if(DMA, irq_index > 1);
+    check_dma_channel_param(channel);
+    return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel);
+}
+
+/*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq0(uint channel) {
+    check_dma_channel_param(channel);
+    hw_set_bits(&dma_hw->ints0, (1u << channel));
+}
+
+/*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq1(uint channel) {
+    check_dma_channel_param(channel);
+    hw_set_bits(&dma_hw->ints1, (1u << channel));
+}
+
+/*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ */
+static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
+    invalid_params_if(DMA, irq_index > 1);
+    check_dma_channel_param(channel);
+    hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel));
+}
+
 /*! \brief  Check if DMA channel is busy
  *  \ingroup hardware_dma
  *

src/rp2_common/hardware_interp/include/hardware/interp.h

@@ -55,7 +55,7 @@ typedef struct {
 } interp_config;
 
 static inline uint interp_index(interp_hw_t *interp) {
-    assert(interp == interp0 || interp == interp1);
+    valid_params_if(INTERP, interp == interp0 || interp == interp1);
     return interp == interp1 ? 1 : 0;
 }
 
@@ -70,6 +70,8 @@ static inline uint interp_index(interp_hw_t *interp) {
  * \param lane The lane number, 0 or 1.
  */
 void interp_claim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_claim interp_claim_lane
 
 /*! \brief Claim the interpolator lanes specified in the mask
  *  \ingroup hardware_interp
@@ -86,6 +88,19 @@ void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask);
  * \param lane The lane number, 0 or 1
  */
 void interp_unclaim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_unclaim interp_unclaim_lane
+
+/*! \brief Determine if an interpolator lane is claimed
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator whose lane to check
+ * \param lane The lane number, 0 or 1
+ * \return true if claimed, false otherwise
+ * \see interp_claim_lane
+ * \see interp_claim_lane_mask
+ */
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane);
 
 /*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask
  *  \ingroup hardware_interp