Fix Risc-V build

Author: will-v-pi

src/rp2_common/pico_crt0/crt0_riscv.S

@@ -30,6 +30,11 @@
 #define PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK (PICO_CRT0_INCLUDE_PICOBIN_BLOCK && !PICO_NO_FLASH)
 #endif
 
+// PICO_CONFIG: PICO_CRT0_NO_DATA_COPY, Whether crt0 should perform the data copies - usually copying from flash into sram, default=1 for no_flash builds, 0 otherwise, type=bool, group=pico_crt0
+#ifndef PICO_CRT0_NO_DATA_COPY
+#define PICO_CRT0_NO_DATA_COPY PICO_NO_FLASH
+#endif
+
 // If vectors are in RAM, we put them in the .data section, so that they are
 // preloaded by _reset_handler (assuming this is not a loaded-in-place
 // binary).
@@ -340,7 +345,7 @@ _call_xip_setup:
 
     // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded
     // in-place by the SRAM load. Still need to clear .bss
-#if !PICO_NO_FLASH
+#if !PICO_CRT0_NO_DATA_COPY
     la a4, data_cpy_table
 
     // assume there is at least one entry
@@ -379,14 +384,25 @@ platform_entry: // symbol for stack traces
     ebreak
     j 1b
 
+#if !PICO_CRT0_NO_DATA_COPY
+#if PICO_NO_FLASH
+data_cpy:
+    // skip copies with same source and destination
+    bne a0, a1, data_cpy_start
+    ret
+#else
+    // go straight into the copy
+    #define data_cpy_start data_cpy
+#endif
 data_cpy_loop:
     lw a0, (a1)
     sw a0, (a2)
     addi a1, a1, 4
     addi a2, a2, 4
-data_cpy:
+data_cpy_start:
     bltu a2, a3, data_cpy_loop
     ret
+#endif
 
 .align 2
 data_cpy_table:
@@ -412,6 +428,10 @@ data_cpy_table:
 .word __scratch_y_start__
 .word __scratch_y_end__
 
+#ifdef PICO_DATA_COPY_EXTRA_SECTIONS_FILE
+#include PICO_DATA_COPY_EXTRA_SECTIONS_FILE
+#endif
+
 .word 0 // null terminator
 
 // ----------------------------------------------------------------------------

src/rp2_common/pico_standard_link/CMakeLists.txt

@@ -184,11 +184,11 @@ if (NOT TARGET pico_standard_link)
                 set(ADDITIONAL_MEMORY "set(ADDITIONAL_MEMORY \"    XIP_RAM(rwx) : ORIGIN = ${XIP_SRAM_BASE}, LENGTH = ${XIP_SRAM_END} - ${XIP_SRAM_BASE}\")" PARENT_SCOPE)
             endfunction()
             target_compile_definitions(${TARGET} PRIVATE PICO_DATA_COPY_EXTRA_SECTIONS_FILE="data_cpy_xip_text.S" PICO_USE_XIP_CACHE_AS_RAM=1)
-            file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/data_cpy_xip_text.S "
+            file(CONFIGURE OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/data_cpy_xip_text.S CONTENT "
 .word __xip_ram_text_source__
 .word __xip_ram_text_start__
 .word __xip_ram_text_end__
-")
+" @ONLY)
             target_include_directories(${TARGET} PRIVATE ${CMAKE_CURRENT_BINARY_DIR})
             if (TYPE STREQUAL "no_flash_using_xip_ram")
                 pico_set_modified_binary_type(${TARGET} sram EXTRAS pico_internal_add_xip_text_section)

test/pico_xip_sram_test/CMakeLists.txt

@@ -2,12 +2,15 @@
 add_executable(pico_xip_sram_test pico_xip_sram_test.c)
 target_link_libraries(pico_xip_sram_test PRIVATE pico_stdlib)
 pico_set_binary_type(pico_xip_sram_test xip_sram)
-pico_minimize_runtime(pico_xip_sram_test INCLUDE PRINTF PRINTF_MINIMAL DEFAULT_ALARM_POOL PANIC)
+pico_minimize_runtime(pico_xip_sram_test INCLUDE PRINTF PRINTF_MINIMAL DEFAULT_ALARM_POOL PANIC FLOAT)
 target_compile_definitions(pico_xip_sram_test PRIVATE PICO_HEAP_SIZE=0x200)
 pico_add_extra_outputs(pico_xip_sram_test)
 
 # Use XIP SRAM for time critical functions
 add_executable(pico_critical_xip_sram_test pico_critical_xip_sram_test.c)
 target_link_libraries(pico_critical_xip_sram_test PRIVATE pico_stdlib pico_multicore hardware_dma)
+if (NOT PICO_RP2040)
+    target_link_libraries(pico_critical_xip_sram_test PRIVATE hardware_riscv_platform_timer)
+endif()
 pico_set_binary_type(pico_critical_xip_sram_test copy_to_ram_using_xip_ram)
 pico_add_extra_outputs(pico_critical_xip_sram_test)

test/pico_xip_sram_test/pico_critical_xip_sram_test.c

@@ -2,34 +2,57 @@
 #include "pico/stdlib.h"
 #include "pico/multicore.h"
 #include "hardware/dma.h"
+#if PICO_RP2040
 #include "hardware/structs/systick.h"
+#else
+#include "hardware/riscv_platform_timer.h"
+#endif
 #include "hardware/structs/busctrl.h"
 
 
 int __time_critical_func(test_func_xip)(void) {
+#if PICO_RP2040
     systick_hw->rvr = 0x00ffffff;
     systick_hw->cvr = 0;
+#else
+    riscv_timer_set_mtimecmp(0xffffffffffffffff);
+    riscv_timer_set_mtime(0);
+#endif
 
     volatile uint32_t i = 0;
     i += 4;
     i += i;
 
+#if PICO_RP2040
     return systick_hw->rvr - systick_hw->cvr;
+#else
+    return riscv_timer_get_mtime();
+#endif
 }
 
 int __not_in_flash_func(test_func_sram)(void) {
+#if PICO_RP2040
     systick_hw->rvr = 0x00ffffff;
     systick_hw->cvr = 0;
+#else
+    riscv_timer_set_mtimecmp(0xffffffffffffffff);
+    riscv_timer_set_mtime(0);
+#endif
 
     volatile uint32_t i = 0;
     i += 4;
     i += i;
 
+#if PICO_RP2040
     return systick_hw->rvr - systick_hw->cvr;
+#else
+    return riscv_timer_get_mtime();
+#endif
 }
 
 
 void core1_entry() {
+#ifndef __riscv
     // Just read memory repeatedly
     pico_default_asm_volatile(
         "1:\n"
@@ -45,6 +68,29 @@ void core1_entry() {
         "b 1b\n"
         : : "i" (SRAM_BASE) : "r0", "r1", "r2", "r3", "r4"
     );
+#else
+    pico_default_asm_volatile(
+        "1:\n"
+        "li a0, %0\n"
+        "lw a1, 0(a0)\n"
+        "lw a2, 4(a0)\n"
+        "lw a3, 8(a0)\n"
+        "lw a4, 12(a0)\n"
+        "addi a0, a0, 16\n"
+        "lw a1, 0(a0)\n"
+        "lw a2, 4(a0)\n"
+        "lw a3, 8(a0)\n"
+        "lw a4, 12(a0)\n"
+        "addi a0, a0, 16\n"
+        "lw a1, 0(a0)\n"
+        "lw a2, 4(a0)\n"
+        "lw a3, 8(a0)\n"
+        "lw a4, 12(a0)\n"
+        "addi a0, a0, 16\n"
+        "j 1b\n"
+        : : "i" (SRAM_BASE) : "a0", "a1", "a2", "a3", "a4"
+    );
+#endif
 }
 
 
@@ -74,7 +120,13 @@ int main(void) {
 
     multicore_launch_core1(core1_entry);
 
+#if PICO_RP2040
     systick_hw->csr = 0x4 | 0x1; // clock source and enable
+#else
+    riscv_timer_set_fullspeed(true);
+    riscv_timer_set_enabled(true);
+    riscv_timer_set_mtimecmp(0xffffffffffffffff);
+#endif
 
     // Give core1 and DMA high priority
     hw_set_bits(&busctrl_hw->priority, BUSCTRL_BUS_PRIORITY_PROC1_BITS | BUSCTRL_BUS_PRIORITY_DMA_R_BITS | BUSCTRL_BUS_PRIORITY_DMA_W_BITS);