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Commit aaae9cf

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switch delay from ms to us
1 parent 25fd5b2 commit aaae9cf

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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

src/rp2_common/hardware_clocks/include/hardware/clocks.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -231,9 +231,9 @@ extern "C" {
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#endif
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#endif // PICO_RP2040 && SYS_CLK_KHZ == 200000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1
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234-
// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_MS, Number of milliseconds to wait after updating regular voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
235-
#ifndef SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_MS
236-
#define SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_MS 1
234+
// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regular voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
235+
#ifndef SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US
236+
#define SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US 1000
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#endif
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239239
#if !defined(PLL_SYS_VCO_FREQ_HZ) || !defined(PLL_SYS_POSTDIV1) || !defined(PLL_SYS_POSTDIV2)

src/rp2_common/pico_runtime_init/runtime_init_clocks.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ void __weak runtime_init_clocks(void) {
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if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
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vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
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// wait for voltage to settle
76-
busy_wait_ms(SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_MS);
76+
busy_wait_us_32(SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US);
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}
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#endif
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// Configure clocks

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