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add PICO_USE_FASTEST_SUPPORTED_CLOCK, and support vreg setting and SYS_CLOCK_MHZ=200 for rp2040 #2285

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Merged
merged 6 commits into from
Feb 18, 2025
Merged

add PICO_USE_FASTEST_SUPPORTED_CLOCK, and support vreg setting and SYS_CLOCK_MHZ=200 for rp2040 #2285

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2d027b1
add PICO_USE_FASTEST_SUPPORTED_CLOCK, and support vreg setting and SY…
kilograham Feb 12, 2025
cfb7f7a
fix BAZEL depeencies
kilograham Feb 17, 2025
459a83b
Small tweaks to keep tools/extract_configs.py happy
lurch Feb 17, 2025
25fd5b2
review tweaks
kilograham Feb 17, 2025
aaae9cf
switch delay from ms to us
kilograham Feb 17, 2025
68eaf25
fix delay after vreg setting to use XOSC clocked CPU
kilograham Feb 17, 2025
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2 changes: 1 addition & 1 deletion src/rp2_common/hardware_clocks/include/hardware/clocks.h
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Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,7 @@ extern "C" {
#endif
#endif // PICO_RP2040 && SYS_CLK_KHZ == 200000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1

// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regular voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regulator voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
#ifndef SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US
#define SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US 1000
#endif
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16 changes: 9 additions & 7 deletions src/rp2_common/pico_runtime_init/runtime_init_clocks.c
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Original file line number Diff line number Diff line change
Expand Up @@ -69,13 +69,6 @@ void __weak runtime_init_clocks(void) {
pll_init(pll_usb, PLL_USB_REFDIV, PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2);
/// \end::pll_init[]

#if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
// wait for voltage to settle
busy_wait_us_32(SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US);
}
#endif
// Configure clocks

// RP2040 CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz
Expand All @@ -94,6 +87,15 @@ void __weak runtime_init_clocks(void) {
0,
XOSC_HZ);

// This must be done after we've configured CLK_REF to XOSC due to the need to time a delay
#if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
// wait for voltage to settle; must use CPU cycles as TIMER is not yet clocked correctly
busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000));
}
#endif

/// \tag::configure_clk_sys[]
// CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz
clock_configure_undivided(clk_sys,
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