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Revert "[AArch64][DebugInfo]Add Target hooks for InstrRef on AArch64 (llvm#165953)"
This reverts commit 44b94a4. Seeing issues in Chromium build /Volumes/Work/s/w/ir/x/w/llvm_build/bin/llc -o - /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir -run-pass=livedebugvalues | /Volumes/Work/s/w/ir/x/w/llvm_build/bin/FileCheck /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir # RUN: at line 8 + /Volumes/Work/s/w/ir/x/w/llvm_build/bin/llc -o - /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir -run-pass=livedebugvalues + /Volumes/Work/s/w/ir/x/w/llvm_build/bin/FileCheck /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir error: YAML:121:3: unknown key 'stackSizePPR' stackSizePPR: 0 ^~~~~~~~~~~~ FileCheck error: '<stdin>' is empty. FileCheck command line: /Volumes/Work/s/w/ir/x/w/llvm_build/bin/FileCheck /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 22 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -2452,10 +2452,11 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
24522452
return false;
24532453
}
24542454

2455-
static bool isFrameLoadOpcode(int Opcode) {
2456-
switch (Opcode) {
2455+
Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2456+
int &FrameIndex) const {
2457+
switch (MI.getOpcode()) {
24572458
default:
2458-
return false;
2459+
break;
24592460
case AArch64::LDRWui:
24602461
case AArch64::LDRXui:
24612462
case AArch64::LDRBui:
@@ -2464,27 +2465,22 @@ static bool isFrameLoadOpcode(int Opcode) {
24642465
case AArch64::LDRDui:
24652466
case AArch64::LDRQui:
24662467
case AArch64::LDR_PXI:
2467-
return true;
2468+
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
2469+
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
2470+
FrameIndex = MI.getOperand(1).getIndex();
2471+
return MI.getOperand(0).getReg();
2472+
}
2473+
break;
24682474
}
2469-
}
24702475

2471-
Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2472-
int &FrameIndex) const {
2473-
if (!isFrameLoadOpcode(MI.getOpcode()))
2474-
return Register();
2475-
2476-
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
2477-
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
2478-
FrameIndex = MI.getOperand(1).getIndex();
2479-
return MI.getOperand(0).getReg();
2480-
}
2481-
return Register();
2476+
return 0;
24822477
}
24832478

2484-
static bool isFrameStoreOpcode(int Opcode) {
2485-
switch (Opcode) {
2479+
Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2480+
int &FrameIndex) const {
2481+
switch (MI.getOpcode()) {
24862482
default:
2487-
return false;
2483+
break;
24882484
case AArch64::STRWui:
24892485
case AArch64::STRXui:
24902486
case AArch64::STRBui:
@@ -2493,63 +2489,14 @@ static bool isFrameStoreOpcode(int Opcode) {
24932489
case AArch64::STRDui:
24942490
case AArch64::STRQui:
24952491
case AArch64::STR_PXI:
2496-
return true;
2497-
}
2498-
}
2499-
2500-
Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2501-
int &FrameIndex) const {
2502-
if (!isFrameStoreOpcode(MI.getOpcode()))
2503-
return Register();
2504-
2505-
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
2506-
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
2507-
FrameIndex = MI.getOperand(1).getIndex();
2508-
return MI.getOperand(0).getReg();
2509-
}
2510-
return Register();
2511-
}
2512-
2513-
Register AArch64InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
2514-
int &FrameIndex) const {
2515-
if (!isFrameStoreOpcode(MI.getOpcode()))
2516-
return Register();
2517-
2518-
if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
2519-
return Reg;
2520-
2521-
SmallVector<const MachineMemOperand *, 1> Accesses;
2522-
if (hasStoreToStackSlot(MI, Accesses)) {
2523-
if (Accesses.size() > 1)
2524-
return Register();
2525-
2526-
FrameIndex =
2527-
cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
2528-
->getFrameIndex();
2529-
return MI.getOperand(0).getReg();
2530-
}
2531-
return Register();
2532-
}
2533-
2534-
Register AArch64InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
2535-
int &FrameIndex) const {
2536-
if (!isFrameLoadOpcode(MI.getOpcode()))
2537-
return Register();
2538-
2539-
if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
2540-
return Reg;
2541-
2542-
SmallVector<const MachineMemOperand *, 1> Accesses;
2543-
if (hasLoadFromStackSlot(MI, Accesses)) {
2544-
if (Accesses.size() > 1)
2545-
return Register();
2546-
2547-
FrameIndex =
2548-
cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
2549-
->getFrameIndex();
2550-
return MI.getOperand(0).getReg();
2492+
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
2493+
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
2494+
FrameIndex = MI.getOperand(1).getIndex();
2495+
return MI.getOperand(0).getReg();
2496+
}
2497+
break;
25512498
}
2552-
return Register();
2499+
return 0;
25532500
}
25542501

25552502
/// Check all MachineMemOperands for a hint to suppress pairing.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -205,15 +205,6 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
205205
Register isStoreToStackSlot(const MachineInstr &MI,
206206
int &FrameIndex) const override;
207207

208-
/// Check for post-frame ptr elimination stack locations as well. This uses a
209-
/// heuristic so it isn't reliable for correctness.
210-
Register isStoreToStackSlotPostFE(const MachineInstr &MI,
211-
int &FrameIndex) const override;
212-
/// Check for post-frame ptr elimination stack locations as well. This uses a
213-
/// heuristic so it isn't reliable for correctness.
214-
Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
215-
int &FrameIndex) const override;
216-
217208
/// Does this instruction set its full destination register to zero?
218209
static bool isGPRZero(const MachineInstr &MI);
219210

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -89,33 +89,33 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
8989
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap:
9090
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
9191
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
92-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
92+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
9393
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
9494
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
95-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
95+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
9696
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
9797
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
9898
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
99-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
99+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
100100
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
101101
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
102102
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
103-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
103+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
104104
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
105105
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
106106
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
107107
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
108-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
108+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
109109
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
110110
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
111111
;
112112
; CHECK-CAS-O0-LABEL: val_compare_and_swap:
113113
; CHECK-CAS-O0: // %bb.0:
114114
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
115115
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
116-
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
116+
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
117117
; CHECK-CAS-O0-NEXT: mov x1, x5
118-
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
118+
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
119119
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
120120
; CHECK-CAS-O0-NEXT: mov x3, x5
121121
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -216,33 +216,33 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
216216
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
217217
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
218218
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
219-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
219+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
220220
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
221221
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
222-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
222+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
223223
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
224224
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
225225
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
226-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
226+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
227227
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
228228
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
229229
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
230-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
230+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
231231
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
232232
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
233233
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
234234
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
235-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
235+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
236236
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
237237
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
238238
;
239239
; CHECK-CAS-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
240240
; CHECK-CAS-O0: // %bb.0:
241241
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
242242
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
243-
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
243+
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
244244
; CHECK-CAS-O0-NEXT: mov x1, x5
245-
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
245+
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
246246
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
247247
; CHECK-CAS-O0-NEXT: mov x3, x5
248248
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -343,33 +343,33 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
343343
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_release_acquire:
344344
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
345345
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
346-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
346+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
347347
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
348348
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
349-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
349+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
350350
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
351351
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
352352
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
353-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
353+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
354354
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
355355
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
356356
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
357-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
357+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
358358
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
359359
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
360360
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
361361
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
362-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
362+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
363363
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
364364
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
365365
;
366366
; CHECK-CAS-O0-LABEL: val_compare_and_swap_release_acquire:
367367
; CHECK-CAS-O0: // %bb.0:
368368
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
369369
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
370-
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
370+
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
371371
; CHECK-CAS-O0-NEXT: mov x1, x5
372-
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
372+
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
373373
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
374374
; CHECK-CAS-O0-NEXT: mov x3, x5
375375
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -470,33 +470,33 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
470470
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic:
471471
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
472472
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
473-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
473+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
474474
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
475475
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
476-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
476+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
477477
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
478478
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
479479
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
480-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
480+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
481481
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
482482
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
483483
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
484-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
484+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
485485
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
486486
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
487487
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
488488
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
489-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
489+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
490490
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
491491
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
492492
;
493493
; CHECK-CAS-O0-LABEL: val_compare_and_swap_monotonic:
494494
; CHECK-CAS-O0: // %bb.0:
495495
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
496496
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
497-
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
497+
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
498498
; CHECK-CAS-O0-NEXT: mov x1, x5
499-
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
499+
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
500500
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
501501
; CHECK-CAS-O0-NEXT: mov x3, x5
502502
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -580,22 +580,22 @@ define void @atomic_load_relaxed(i64, i64, ptr %p, ptr %p2) {
580580
; CHECK-OUTLINE-LLSC-O0-LABEL: atomic_load_relaxed:
581581
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
582582
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
583-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
583+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
584584
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
585585
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
586586
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x4, x2
587-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
587+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
588588
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, xzr
589589
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x3
590590
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
591591
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x3
592592
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_relax
593-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Reload
593+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Folded Reload
594594
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
595595
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x0
596596
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
597597
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x3]
598-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
598+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
599599
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
600600
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
601601
;
@@ -690,17 +690,17 @@ define i128 @val_compare_and_swap_return(ptr %p, i128 %oldval, i128 %newval) {
690690
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_return:
691691
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
692692
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
693-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
693+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
694694
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
695695
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
696-
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
696+
; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
697697
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
698698
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
699699
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
700-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
700+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
701701
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
702702
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
703-
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
703+
; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
704704
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
705705
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
706706
;

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