Fix unused unsafe for mipsel and riscv32

Author: Jiajie Chen

kernel/src/arch/mipsel/board/malta/mod.rs

@@ -19,11 +19,9 @@ pub fn init_serial_early() {
     // initialize serial driver
     serial::init(0xbf000900);
     // Enable serial interrupt
-    unsafe {
-        let mut status = cp0::status::read();
-        status.enable_hard_int2();
-        cp0::status::write(status);
-    }
+    let mut status = cp0::status::read();
+    status.enable_hard_int2();
+    cp0::status::write(status);
     println!("Hello QEMU Malta!");
 }
 

kernel/src/arch/mipsel/context.rs

@@ -299,7 +299,7 @@ impl Context {
     /// The SATP register will be set to `satp`.
     /// All the other registers are same as the original.
     pub unsafe fn new_fork(tf: &TrapFrame, kstack_top: usize, satp: usize) -> Self {
-        let tls = unsafe { *(_cur_tls as *const usize) };
+        let tls = *(_cur_tls as *const usize);
         InitStack {
             context: ContextData::new(satp, tls),
             tf: {

kernel/src/arch/mipsel/interrupt.rs

@@ -18,23 +18,21 @@ pub fn init() {
     extern "C" {
         fn trap_entry();
     }
-    unsafe {
-        // Set the exception vector address
-        cp0::ebase::write_u32(trap_entry as u32);
-        println!("Set ebase = {:x}", trap_entry as u32);
+    // Set the exception vector address
+    cp0::ebase::write_u32(trap_entry as u32);
+    println!("Set ebase = {:x}", trap_entry as u32);
 
-        let mut status = cp0::status::read();
-        // Enable IPI
-        status.enable_soft_int0();
-        status.enable_soft_int1();
-        // Enable clock interrupt
-        status.enable_hard_int5();
-        // Enable serial interrupt
-        #[cfg(feature = "board_thinpad")]
-        status.enable_hard_int0();
+    let mut status = cp0::status::read();
+    // Enable IPI
+    status.enable_soft_int0();
+    status.enable_soft_int1();
+    // Enable clock interrupt
+    status.enable_hard_int5();
+    // Enable serial interrupt
+    #[cfg(feature = "board_thinpad")]
+    status.enable_hard_int0();
 
-        cp0::status::write(status);
-    }
+    cp0::status::write(status);
     info!("interrupt: init end");
 }
 

kernel/src/arch/mipsel/paging.rs

@@ -83,9 +83,7 @@ pub fn root_page_table_buffer() -> &'static mut MIPSPageTable {
 /// implementation for the Entry trait in /crate/memory/src/paging/mod.rs
 impl Entry for PageEntry {
     fn update(&mut self) {
-        unsafe {
-            TLBEntry::clear_all();
-        }
+        TLBEntry::clear_all();
     }
     fn accessed(&self) -> bool {
         self.0.flags().contains(EF::ACCESSED)
@@ -156,7 +154,7 @@ impl PageTableImpl {
         ManuallyDrop::new(PageTableImpl {
             page_table: TwoLevelPageTable::new(table),
             root_frame: frame,
-            entry: unsafe { core::mem::MaybeUninit::zeroed().assume_init() },
+            entry: core::mem::MaybeUninit::zeroed().assume_init(),
         })
     }
 
@@ -199,9 +197,7 @@ impl PageTableExt for PageTableImpl {
     }
 
     fn flush_tlb() {
-        unsafe {
-            TLBEntry::clear_all();
-        }
+        TLBEntry::clear_all();
     }
 }
 

kernel/src/arch/riscv32/paging.rs

@@ -158,7 +158,7 @@ impl PageTableImpl {
         ManuallyDrop::new(PageTableImpl {
             page_table: TopLevelPageTable::new(table, PHYSICAL_MEMORY_OFFSET),
             root_frame: frame,
-            entry: unsafe { core::mem::MaybeUninit::zeroed().assume_init() },
+            entry: core::mem::MaybeUninit::zeroed().assume_init(),
         })
     }
     /// The method for getting the kernel page table.