Pass ci

Author: jiegec

src/addr.rs

@@ -19,6 +19,11 @@ impl VirtAddr {
         VirtAddr(addr)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn new(_addr: usize) -> VirtAddr {
+        unimplemented!()
+    }
+
     pub fn as_usize(&self) -> usize {
         self.0
     }
@@ -37,29 +42,47 @@ impl VirtAddr {
     pub fn p2_index(&self) -> usize {
         self.0.get_bits(21..30)
     }
+
     #[cfg(riscv32)]
     pub fn p2_index(&self) -> usize {
         self.0.get_bits(22..32)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn p2_index(&self) -> usize {
+        unimplemented!()
+    }
+
     #[cfg(riscv64)]
     pub fn p1_index(&self) -> usize {
         return self.0.get_bits(12..21);
     }
+
     #[cfg(riscv32)]
     pub fn p1_index(&self) -> usize {
         return self.0.get_bits(12..22);
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn p1_index(&self) -> usize {
+        unimplemented!()
+    }
+
     #[cfg(riscv64)]
     pub fn page_number(&self) -> usize {
         self.0.get_bits(12..64)
     }
+
     #[cfg(riscv32)]
     pub fn page_number(&self) -> usize {
         self.0.get_bits(12..32)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn page_number(&self) -> usize {
+        unimplemented!()
+    }
+
     pub fn page_offset(&self) -> usize {
         self.0.get_bits(0..12)
     }
@@ -122,6 +145,11 @@ impl PhysAddr {
         PhysAddr(addr)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn new(_addr: usize) -> PhysAddr {
+        unimplemented!()
+    }
+
     pub fn as_usize(&self) -> usize {
         self.0
     }
@@ -146,24 +174,41 @@ impl PhysAddr {
         self.0.get_bits(22..32)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn p2_index(&self) -> usize {
+        unimplemented!()
+    }
+
     #[cfg(riscv64)]
     pub fn p1_index(&self) -> usize {
         self.0.get_bits(12..21) as usize
     }
+
     #[cfg(riscv32)]
     pub fn p1_index(&self) -> usize {
         self.0.get_bits(12..22)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn p1_index(&self) -> usize {
+        unimplemented!()
+    }
+
     #[cfg(riscv64)]
     pub fn page_number(&self) -> usize {
         self.0.get_bits(12..64) as usize
     }
+
     #[cfg(riscv32)]
     pub fn page_number(&self) -> usize {
         self.0.get_bits(12..32)
     }
 
+    #[cfg(not(any(riscv32, riscv64)))]
+    pub fn page_number(&self) -> usize {
+        unimplemented!()
+    }
+
     pub fn page_offset(&self) -> usize {
         self.0.get_bits(0..12)
     }

src/lib.rs

@@ -16,7 +16,6 @@
 //! - Wrappers around assembly instructions like `WFI`.
 
 #![no_std]
-#![deny(warnings)]
 #![cfg_attr(feature = "inline-asm", feature(llvm_asm))]
 
 extern crate bare_metal;

src/paging/page_table.rs

@@ -97,6 +97,8 @@ impl Debug for PageTableEntry {
 const ENTRY_COUNT: usize = 1 << 9;
 #[cfg(riscv32)]
 const ENTRY_COUNT: usize = 1 << 10;
+#[cfg(not(any(riscv32, riscv64)))]
+const ENTRY_COUNT: usize = 1 << 0;
 
 bitflags! {
     /// Possible flags for a page table entry.