Merge remote-tracking branch 'upstream/master'

Author: yesh0

.github/bors.toml

@@ -1,4 +1,10 @@
 block_labels = ["needs-decision"]
 delete_merged_branches = true
 required_approvals = 1
-status = ["continuous-integration/travis-ci/push"]
+status = [
+    "ci-linux (stable)",
+    "ci-linux (1.59.0)",
+    "build-other (macOS-latest)",
+    "build-other (windows-latest)",
+    "Rustfmt"
+]

.github/workflows/ci.yaml

@@ -0,0 +1,59 @@
+on:
+  push:
+    branches: [ staging, trying, master ]
+  pull_request:
+
+name: Continuous integration
+
+jobs:
+  ci-linux:
+    runs-on: ubuntu-20.04
+    continue-on-error: ${{ matrix.experimental || false }}
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.59.0
+        rust: [nightly, stable, 1.59.0]
+
+        include:
+          # Nightly is only for reference and allowed to fail
+          - rust: nightly
+            experimental: true
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: ${{ matrix.rust }}
+          override: true
+      - name: Install all Rust targets for ${{ matrix.rust }}
+        run: rustup target install --toolchain=${{ matrix.rust }} x86_64-unknown-linux-gnu riscv32imac-unknown-none-elf riscv64imac-unknown-none-elf riscv64gc-unknown-none-elf
+      - name: Install riscv gcc
+        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
+      - name: Run CI script for x86_64-unknown-linux-gnu under ${{ matrix.rust }}
+        run: cargo check --target x86_64-unknown-linux-gnu
+      - name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
+        run: cargo check --target riscv32imac-unknown-none-elf
+      - name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
+        run: cargo check --target riscv64imac-unknown-none-elf
+      - name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
+        run: cargo check --target riscv64gc-unknown-none-elf
+
+  # On macOS and Windows, we at least make sure that the crate builds and links.
+  build-other:
+    strategy:
+      matrix:
+        os:
+          - macOS-latest
+          - windows-latest
+    runs-on: ${{ matrix.os }}
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - name: Build crate for host OS
+        run: cargo build

.github/workflows/rustfmt.yaml

@@ -0,0 +1,24 @@
+
+on:
+  push:
+    branches: [ staging, trying, master ]
+  pull_request:
+
+name: Code formatting check
+
+jobs:
+  fmt:
+    name: Rustfmt
+    runs-on: ubuntu-20.04
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+          components: rustfmt
+      - uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check

.gitignore

@@ -1,5 +1,2 @@
 Cargo.lock
 target/
-bin/*.after
-bin/*.before
-bin/*.o

.travis.yml

@@ -7,6 +7,56 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Fixed
+
+- Fix `asm::delay()` to ensure count register is always reloaded
+
+## [v0.8.0] - 2022-04-20
+
+### Added
+
+- Add `#[cfg(riscv32)]` to `pmpcfg1` and `pmpcfg3` modules
+- Add enums `Range`, `Permission` for PMP configuration
+- Add `set_pmp()` and `clear_pmp()` functions to pmpcfg(x) modules
+- Add struct `Pmpcsr` and is returned from `pmpcfgx::read()`
+- Add `singleton!` macro
+- Add delay structure and methods using embedded-hal traits and `mcycle` register
+- Add `asm::delay()` function for assembly-based busy-loops
+- Add `asm::nop()`, a wrapper for implementing a `nop` instruction
+- Add missing `#[inline]` attribute to register reads, type conversations and `interrupt::free`
+
+### Changed
+
+- Use new `asm!` instead of `llvm_asm!`
+- Change `pmpcfgx::read()` macro to `read_csr_as!()` from `read_csr_as_usize!()`
+- Inline assembly is now always used
+- Update Minimum Supported Rust Version to 1.59
+
+### Fixed
+
+- Fix `sfence.vma` operand order
+
+### Removed
+
+- Remove `inline-asm` feature which is now always enabled
+
+## [v0.7.0] - 2021-07-29
+
+### Added
+
+- Add `medeleg` register
+- Add `cycle[h]`, `instret[h]` and `mcounteren`
+- Add additional binaries for floating-point ABIs
+- Add support for `mxr`
+- Add support for `mprv`
+
+### Changed
+
+- Fix `scause::set`
+- Various formatting and comment fixes
+- Update `bare-metal` to `v1.0.0` removing `Nr` trait
+- Build targets on `docs.rs` are now RISC-V targets other than default ones
+
 ## [v0.6.0] - 2020-06-20
 
 ### Changed
@@ -39,7 +89,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Fixed MSRV by restricting the upper bound of `bare-metal` version
 
-[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.6.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.8.0...HEAD
+[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.8.0
+[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.0...v0.7.0
 [v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
 [v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
 [v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5

CHANGELOG.md

@@ -2,7 +2,7 @@
 
 ## Conduct
 
-**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team)
+**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team)
 
 * We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic.
 * On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all.

CODE_OF_CONDUCT.md

@@ -1,21 +1,25 @@
 [package]
 name = "riscv"
-version = "0.6.0"
+version = "0.8.0"
+edition = "2021"
+rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 
+[package.metadata.docs.rs]
+default-target = "riscv64imac-unknown-none-elf"
+targets = [
+    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
+    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
+]
+
 [dependencies]
-bare-metal = "0.2.5"
+bare-metal = "1.0.0"
 bitflags = "1.0"
 bit_field = "0.10.0"
 log = "0.4"
-
-[build-dependencies]
-riscv-target = "0.1.2"
-
-[features]
-inline-asm = []
+embedded-hal = "0.2.6"

Cargo.toml

@@ -12,12 +12,12 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.42.0 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License
 
-Copyright 2019-2020 [RISC-V team][team]
+Copyright 2019-2022 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice
@@ -38,4 +38,4 @@ Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
 [CoC]: CODE_OF_CONDUCT.md
-[team]: https://github.com/rust-embedded/wg#the-riscv-team
+[team]: https://github.com/rust-embedded/wg#the-risc-v-team