rename simm12 to simm12_lo per llvm#160380

realqhc · realqhc · commit 2a907f40be10 · 2025-11-29T17:50:43.000+11:00
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -709,8 +709,8 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
 
 let Predicates = [HasVendorXCVelw, IsRV32] in {
   def : Pat<(int_riscv_cv_elw_elw (XLenVT GPR:$rs1)), (PseudoCV_ELW GPR:$rs1)>;
-  def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
-            (CV_ELW GPR:$rs1, simm12:$imm12)>;
+  def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12_lo:$imm12)),
+            (CV_ELW GPR:$rs1, simm12_lo:$imm12)>;
 }
 
 multiclass PatCoreVBitManip<Intrinsic intr> {

Original file line number	Diff line number	Diff line change
`@@ -709,8 +709,8 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {`
`709`	`709`
`710`	`710`	`let Predicates = [HasVendorXCVelw, IsRV32] in {`
`711`	`711`	`def : Pat<(int_riscv_cv_elw_elw (XLenVT GPR:$rs1)), (PseudoCV_ELW GPR:$rs1)>;`
`712`		`- def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),`
`713`		`- (CV_ELW GPR:$rs1, simm12:$imm12)>;`
	`712`	`+ def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12_lo:$imm12)),`
	`713`	`+ (CV_ELW GPR:$rs1, simm12_lo:$imm12)>;`
`714`	`714`	`}`
`715`	`715`
`716`	`716`	`multiclass PatCoreVBitManip<Intrinsic intr> {`