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rtl: update spi miso timing
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5 files changed

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‎README.md‎

Lines changed: 51 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -24,83 +24,85 @@ NeoPixel LED Controller based on MAX10 FPGA.
2424
| spi_miso_o | PIN_P9 | neopixel_code_o[1] | PIN_P3 | neopixel_code_o[9] | PIN_A5 |
2525
| - | | neopixel_code_o[0] | PIN_M4 | neopixel_code_o[8] | PIN_B4 |
2626

27-
* SPI slave mode: F_MAX=30MHz, CPOL=0, CPHA=0, MSB first
27+
* SPI slave mode: F_MAX=20MHz, CPOL=0, CPHA=0, MSB first
2828

2929
## Commands
3030

3131
### CONF_WR
3232

33-
| Inst / Para | D/C | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
34-
| :---------: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
35-
| CONF_WR | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 2Ah |
36-
| 1st Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
37-
| 2nd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
38-
| 3rd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
39-
| 4th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
40-
| 5th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
41-
| 6th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
33+
| Inst / Para | D/C | R/W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
34+
| :---------: | --: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
35+
| CONF_WR | 0 | W | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 2Ah |
36+
| 1st Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
37+
| 2nd Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
38+
| 3rd Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
39+
| 4th Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
40+
| 5th Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
41+
| 6th Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
4242

4343
* 1st Param: T0H time (10 ns), range: 0 - 255
4444
* 2nd Param: T0L time (10 ns), range: 0 - 255
4545
* 3rd Param: T1H time (10 ns), range: 0 - 255
4646
* 4th Param: T1L time (10 ns), range: 0 - 255
47-
* 5th Param: channel length, range: 0 - 255
48-
* 6th Param: channel count, range: 0 - 15
47+
* 5th Param: Channel length, range: 0 - 255
48+
* 6th Param: Channel count, range: 0 - 15
4949

5050
### ADDR_WR
5151

52-
| Inst / Para | D/C | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
53-
| :---------: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
54-
| ADDR_WR | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 2Bh |
55-
| 1st Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
56-
| ... | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
57-
| Nth Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
52+
| Inst / Para | D/C | R/W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
53+
| :---------: | --: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
54+
| ADDR_WR | 0 | W | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 2Bh |
55+
| 1st Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
56+
| ... | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
57+
| Nth Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
5858

59-
* 1st Param: channel 0, the next pointer of the 1st color data, range: 0 - 255
60-
* 2nd Param: channel 0, the next pointer of the 2nd color data, range: 0 - 255
59+
* 1st Param: Channel 0, the next pointer of the 1st color data, range: 0 - 255
60+
* 2nd Param: Channel 0, the next pointer of the 2nd color data, range: 0 - 255
6161
* ...
6262
* Nth Param: ...
6363

6464
* N_MAX = 256 x 16 = 4096
6565

6666
### DATA_WR
6767

68-
| Inst / Para | D/C | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
69-
| :---------: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
70-
| DATA_WR | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 2Ch |
71-
| 1st Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
72-
| ... | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
73-
| Nth Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
74-
75-
* 1st Param: channel 0, the 1st color data, byte 2, range: 0 - 255
76-
* 2nd Param: channel 0, the 1st color data, byte 1, range: 0 - 255
77-
* 3rd Param: channel 0, the 1st color data, byte 0, range: 0 - 255
78-
* 4th Param: channel 0, the 2nd color data, byte 2, range: 0 - 255
68+
| Inst / Para | D/C | R/W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
69+
| :---------: | --: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
70+
| DATA_WR | 0 | W | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 2Ch |
71+
| 1st Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
72+
| ... | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
73+
| Nth Param | 1 | W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
74+
75+
* 1st Param: Channel 0, the 1st color data, byte 2, range: 0 - 255
76+
* 2nd Param: Channel 0, the 1st color data, byte 1, range: 0 - 255
77+
* 3rd Param: Channel 0, the 1st color data, byte 0, range: 0 - 255
78+
* 4th Param: Channel 0, the 2nd color data, byte 2, range: 0 - 255
7979
* ...
8080
* Nth Param: ...
8181

8282
* N_MAX = 256 x 16 x 3 = 12288
8383

8484
### INFO_RD
8585

86-
| Inst / Para | D/C | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
87-
| :---------: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
88-
| INFO_RD | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 3Ah |
89-
| 1st Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
90-
| 2nd Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
91-
| 3rd Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
92-
| 4th Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
93-
| 5th Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
94-
| 6th Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
95-
| 7th Data | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
96-
97-
* 1st Data: RTL revision, major: {D7..D4}, minor: {D3..D0}
98-
* 2nd Data: T0H time (10 ns), range: 0 - 255
99-
* 3rd Data: T0L time (10 ns), range: 0 - 255
100-
* 4th Data: T1H time (10 ns), range: 0 - 255
101-
* 5th Data: T1L time (10 ns), range: 0 - 255
102-
* 6th Data: channel length, range: 0 - 255
103-
* 7th Data: channel count, range: 0 - 15
86+
| Inst / Para | D/C | R/W | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | HEX |
87+
| :---------: | --: | --: | -: | -: | -: | -: | -: | -: | -: | -: | --: |
88+
| INFO_RD | 0 | W | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 3Ah |
89+
| 1st Data | 1 | R | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00h |
90+
| 2nd Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
91+
| 3rd Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
92+
| 4th Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
93+
| 5th Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
94+
| 6th Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
95+
| 7th Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
96+
| 7th Data | 1 | R | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
97+
98+
* 1st Data: Dummy byte, 0x00
99+
* 2nd Data: RTL revision, major: {D7..D4}, minor: {D3..D0}
100+
* 3rd Data: T0H time (10 ns), range: 0 - 255
101+
* 4th Data: T0L time (10 ns), range: 0 - 255
102+
* 5th Data: T1H time (10 ns), range: 0 - 255
103+
* 6th Data: T1L time (10 ns), range: 0 - 255
104+
* 7th Data: Channel length, range: 0 - 255
105+
* 8th Data: Channel count, range: 0 - 15
104106

105107
## Preparing
106108

‎rtl/channel_ctl.sv‎

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,11 @@ begin
8080
end else begin
8181
if (spi_byte_vld_i) begin
8282
if (!dc_i) begin // Command
83+
rd_addr <= 3'h0;
8384
wr_addr <= 8'h00;
8485

8586
case (spi_byte_data_i)
8687
CUBE0414_CONF_WR: begin // Write Reg Conf
87-
rd_addr <= 3'h0;
88-
8988
addr_en <= 1'b0;
9089
data_en <= 3'b000;
9190

@@ -94,8 +93,6 @@ begin
9493
data_wr <= 16'h0000;
9594
end
9695
CUBE0414_ADDR_WR: begin // Write RAM Addr
97-
rd_addr <= 3'h0;
98-
9996
addr_en <= 1'b1;
10097
data_en <= 3'b000;
10198

@@ -104,8 +101,6 @@ begin
104101
data_wr <= 16'h0001;
105102
end
106103
CUBE0414_DATA_WR: begin // Write RAM Data
107-
rd_addr <= 3'h0;
108-
109104
addr_en <= 1'b0;
110105
data_en <= 3'b100;
111106

@@ -114,8 +109,6 @@ begin
114109
data_wr <= 16'h0001;
115110
end
116111
CUBE0414_INFO_RD: begin // Read Chip Info
117-
rd_addr <= 3'h1;
118-
119112
addr_en <= 1'b0;
120113
data_en <= 3'b000;
121114

@@ -124,8 +117,6 @@ begin
124117
data_wr <= 16'h0000;
125118
end
126119
default: begin
127-
rd_addr <= 3'h0;
128-
129120
addr_en <= 1'b0;
130121
data_en <= 3'b000;
131122

‎rtl/spi_slave.sv‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,8 @@ logic spi_sclk;
2626
logic [2:0] bit_sel;
2727
logic bit_mosi;
2828

29-
logic byte_vld, byte_next;
29+
logic byte_vld;
30+
logic [1:0] byte_rdy;
3031

3132
logic [7:0] byte_mosi;
3233
logic [7:0] byte_miso;
@@ -48,20 +49,20 @@ begin
4849
bit_sel <= 3'h0;
4950
bit_mosi <= 1'b0;
5051

51-
byte_vld <= 1'b0;
52-
byte_next <= 1'b0;
52+
byte_vld <= 1'b0;
53+
byte_rdy <= 2'b00;
5354

5455
byte_mosi <= 8'h00;
5556
byte_miso <= 8'h00;
5657
end else begin
5758
bit_sel <= spi_cs_n_i ? 3'h0 : bit_sel + spi_sclk;
5859
bit_mosi <= spi_mosi_i;
5960

60-
byte_vld <= spi_sclk & (bit_sel == 3'h7);
61-
byte_next <= byte_vld;
61+
byte_vld <= spi_sclk & (bit_sel == 3'h7);
62+
byte_rdy <= {byte_rdy[0], byte_vld};
6263

6364
byte_mosi <= spi_sclk ? {byte_mosi[6:0], bit_mosi} : byte_mosi;
64-
byte_miso <= byte_next ? spi_byte_data_i : (spi_sclk ? {byte_miso[6:0], 1'b0} : byte_miso);
65+
byte_miso <= byte_rdy[1] ? spi_byte_data_i : (spi_sclk ? {byte_miso[6:0], 1'b0} : byte_miso);
6566
end
6667
end
6768

‎sim/test_spi_slave.sv‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -64,78 +64,78 @@ always begin
6464
#50 spi_cs_n_i <= 1'b0;
6565

6666
// 0x2A
67-
#12 spi_sclk_i <= 1'b0;
67+
#15 spi_sclk_i <= 1'b0;
6868
spi_mosi_i <= 1'b0; // BIT7
69-
#12 spi_sclk_i <= 1'b1;
69+
#15 spi_sclk_i <= 1'b1;
7070

71-
#12 spi_sclk_i <= 1'b0;
71+
#15 spi_sclk_i <= 1'b0;
7272
spi_mosi_i <= 1'b0; // BIT6
73-
#12 spi_sclk_i <= 1'b1;
73+
#15 spi_sclk_i <= 1'b1;
7474

75-
#12 spi_sclk_i <= 1'b0;
75+
#15 spi_sclk_i <= 1'b0;
7676
spi_mosi_i <= 1'b1; // BIT5
77-
#12 spi_sclk_i <= 1'b1;
77+
#15 spi_sclk_i <= 1'b1;
7878

79-
#12 spi_sclk_i <= 1'b0;
79+
#15 spi_sclk_i <= 1'b0;
8080
spi_mosi_i <= 1'b0; // BIT4
81-
#12 spi_sclk_i <= 1'b1;
81+
#15 spi_sclk_i <= 1'b1;
8282

83-
#12 spi_sclk_i <= 1'b0;
83+
#15 spi_sclk_i <= 1'b0;
8484
spi_mosi_i <= 1'b1; // BIT3
85-
#12 spi_sclk_i <= 1'b1;
85+
#15 spi_sclk_i <= 1'b1;
8686

87-
#12 spi_sclk_i <= 1'b0;
87+
#15 spi_sclk_i <= 1'b0;
8888
spi_mosi_i <= 1'b0; // BIT2
89-
#12 spi_sclk_i <= 1'b1;
89+
#15 spi_sclk_i <= 1'b1;
9090

91-
#12 spi_sclk_i <= 1'b0;
91+
#15 spi_sclk_i <= 1'b0;
9292
spi_mosi_i <= 1'b1; // BIT1
93-
#12 spi_sclk_i <= 1'b1;
93+
#15 spi_sclk_i <= 1'b1;
9494

95-
#12 spi_sclk_i <= 1'b0;
95+
#15 spi_sclk_i <= 1'b0;
9696
spi_mosi_i <= 1'b0; // BIT0
97-
#12 spi_sclk_i <= 1'b1;
97+
#15 spi_sclk_i <= 1'b1;
9898

9999
// 0x2B
100-
#12 spi_sclk_i <= 1'b0;
100+
#15 spi_sclk_i <= 1'b0;
101101
spi_mosi_i <= 1'b0; // BIT7
102-
#12 spi_sclk_i <= 1'b1;
102+
#15 spi_sclk_i <= 1'b1;
103103

104-
#12 spi_sclk_i <= 1'b0;
104+
#15 spi_sclk_i <= 1'b0;
105105
spi_mosi_i <= 1'b0; // BIT6
106-
#12 spi_sclk_i <= 1'b1;
106+
#15 spi_sclk_i <= 1'b1;
107107

108-
#12 spi_sclk_i <= 1'b0;
108+
#15 spi_sclk_i <= 1'b0;
109109
spi_mosi_i <= 1'b1; // BIT5
110-
#12 spi_sclk_i <= 1'b1;
110+
#15 spi_sclk_i <= 1'b1;
111111

112-
#12 spi_sclk_i <= 1'b0;
112+
#15 spi_sclk_i <= 1'b0;
113113
spi_mosi_i <= 1'b0; // BIT4
114-
#12 spi_sclk_i <= 1'b1;
114+
#15 spi_sclk_i <= 1'b1;
115115

116-
#12 spi_sclk_i <= 1'b0;
116+
#15 spi_sclk_i <= 1'b0;
117117
spi_mosi_i <= 1'b1; // BIT3
118-
#12 spi_sclk_i <= 1'b1;
118+
#15 spi_sclk_i <= 1'b1;
119119

120-
#12 spi_sclk_i <= 1'b0;
120+
#15 spi_sclk_i <= 1'b0;
121121
spi_mosi_i <= 1'b0; // BIT2
122-
#12 spi_sclk_i <= 1'b1;
122+
#15 spi_sclk_i <= 1'b1;
123123

124-
#12 spi_sclk_i <= 1'b0;
124+
#15 spi_sclk_i <= 1'b0;
125125
spi_mosi_i <= 1'b1; // BIT1
126-
#12 spi_sclk_i <= 1'b1;
126+
#15 spi_sclk_i <= 1'b1;
127127

128-
#12 spi_sclk_i <= 1'b0;
128+
#15 spi_sclk_i <= 1'b0;
129129
spi_mosi_i <= 1'b1; // BIT0
130-
#12 spi_sclk_i <= 1'b1;
130+
#15 spi_sclk_i <= 1'b1;
131131

132132
for (integer i = 0; i < 24; i++) begin
133-
#12 spi_sclk_i <= 1'b0;
133+
#15 spi_sclk_i <= 1'b0;
134134
spi_mosi_i <= 1'b0;
135-
#12 spi_sclk_i <= 1'b1;
135+
#15 spi_sclk_i <= 1'b1;
136136
end
137137

138-
#12 spi_sclk_i <= 1'b0;
138+
#15 spi_sclk_i <= 1'b0;
139139

140140
#25 spi_cs_n_i <= 1'b1;
141141

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