diff --git a/.gitignore b/.gitignore index 777461401..e8e47462d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,3 @@ -target -/config.toml -.gitlab-ci-local/ +target +/config.toml +.gitlab-ci-local/ diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f3efafbee..8cee6d99d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,30 +1,30 @@ -image: "redoxos/redoxer:latest" - -variables: - GIT_SUBMODULE_STRATEGY: recursive - -stages: - - host - - build - - test - # TODO: benchmarks and profiling (maybe manually enabled for relevant MRs)? - -build: - stage: build - script: - - mkdir -p target/${ARCH} - - TARGET=${ARCH}-unknown-redox redoxer env make BUILD=target/${ARCH} - parallel: - matrix: - - ARCH: [x86_64, i686, aarch64, riscv64gc] - -fmt: - stage: host - script: - - rustup component add rustfmt-preview - - cargo fmt -- --check - -unit_test: - stage: test - script: - - TARGET=x86_64-unknown-redox redoxer test +image: "redoxos/redoxer:latest" + +variables: + GIT_SUBMODULE_STRATEGY: recursive + +stages: + - host + - build + - test + # TODO: benchmarks and profiling (maybe manually enabled for relevant MRs)? + +build: + stage: build + script: + - mkdir -p target/${ARCH} + - TARGET=${ARCH}-unknown-redox redoxer env make BUILD=target/${ARCH} + parallel: + matrix: + - ARCH: [x86_64, i686, aarch64, riscv64gc] + +fmt: + stage: host + script: + - rustup component add rustfmt-preview + - cargo fmt -- --check + +unit_test: + stage: test + script: + - TARGET=x86_64-unknown-redox redoxer test diff --git a/.gitmodules b/.gitmodules index 0a0f6ac82..e723d989a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,11 +1,11 @@ -[submodule "slab_allocator"] - path = slab_allocator - url = https://gitlab.redox-os.org/redox-os/slab_allocator -[submodule "rmm"] - path = rmm - url = https://gitlab.redox-os.org/redox-os/rmm.git - branch = master -[submodule "redox-path"] - path = redox-path - url = https://gitlab.redox-os.org/redox-os/redox-path.git - branch = main +[submodule "slab_allocator"] + path = slab_allocator + url = https://gitlab.redox-os.org/redox-os/slab_allocator +[submodule "rmm"] + path = rmm + url = https://gitlab.redox-os.org/redox-os/rmm.git + branch = master +[submodule "redox-path"] + path = redox-path + url = https://gitlab.redox-os.org/redox-os/redox-path.git + branch = main diff --git a/.helix/config.toml b/.helix/config.toml index a1ec3e0a6..7ae9b1506 100644 --- a/.helix/config.toml +++ b/.helix/config.toml @@ -1,2 +1,2 @@ -[editor] -auto-format = false +[editor] +auto-format = false diff --git a/.helix/languages.toml b/.helix/languages.toml index c86c7b8a5..1606824b8 100644 --- a/.helix/languages.toml +++ b/.helix/languages.toml @@ -1,13 +1,13 @@ -[[language]] -name = "rust" - -[[language-server.rust-analyzer.config.cargo]] -extraEnv = ["RUST_TARGET_PATH=targets"] -# Select one of targets to make lsp work for your confguration -# Do not commit this change -# TODO: find a better way to do this -# target = "aarch64-unknown-kernel" - -[[language-server.rust-analyzer.config.check]] -targets = ["x86_64-unknown-kernel", "i686-unknown-kernel", "aarch64-unknown-kernel"] - +[[language]] +name = "rust" + +[[language-server.rust-analyzer.config.cargo]] +extraEnv = ["RUST_TARGET_PATH=targets"] +# Select one of targets to make lsp work for your confguration +# Do not commit this change +# TODO: find a better way to do this +# target = "aarch64-unknown-kernel" + +[[language-server.rust-analyzer.config.check]] +targets = ["x86_64-unknown-kernel", "i686-unknown-kernel", "aarch64-unknown-kernel"] + diff --git a/ARM-AARCH64-PORT-OUTLINE.md b/ARM-AARCH64-PORT-OUTLINE.md index 8ae61e196..7e53ff5d8 100644 --- a/ARM-AARCH64-PORT-OUTLINE.md +++ b/ARM-AARCH64-PORT-OUTLINE.md @@ -1,79 +1,79 @@ -# Porting the core Redox kernel to arm AArch64: An outline - -## Intro - -This document is [my](https://github.com/raw-bin) attempt at: - -* Capturing thinking on the work needed for a core Redox kernel port -* Sharing progress with the community as things evolve -* Creating a template that can be used for ports to other architectures - -Core Redox kernel means everything needed to get to a non-graphical console-only multi-user shell. - -Only the 64-bit execution state (AArch64) with the 64-bit instruction set architecture (A64) shall be supported for the moment. For more background/context read [this](https://developer.arm.com/products/architecture/a-profile/docs/den0024/latest/introduction). - -This document is intended to be kept *live*. It will be updated to reflect the current state of work and any feedback received. - -It is hard~futile to come up with a strict sequence of work for such ports but this document is a reasonable template to follow. - -## Intended target platform - -The primary focus is on [qemu's virt machine platform emulation for the AArch64 architecture](https://github.com/qemu/qemu/blob/master/hw/arm/virt.c#L127). - -Targeting a virtual platform is a convenient way to bring up the mechanics of architectural support and makes the jump to silicon easier. The preferred boot chain for AArch64 (explained later) is well supported on this platform and boot-over-tftp from localhost makes the debug cycle very efficient. - -Once the core kernel port is complete a similar follow on document will be created that is dedicated to silicon bring-up. - -## Boot protocol elements - -Item | Notes ------|------- -[Linux kernel boot protocol for AArch64](https://www.kernel.org/doc/Documentation/arm64/booting.txt) | The linked document describes assumptions made from the bootloader which are field tested and worthwhile to have for Redox an AArch64.
The intent is to consider most of the document except anything tied to the Linux kernel itself. -[Flattened Device Tree](https://elinux.org/Device_Tree_Reference) | FDT binary blobs supplied by the bootloader shall provide the Redox kernel with misc platform \{memory, interrupt, devicemem} maps. Qemu's virt machine platform synthetically creates an FDT blob at a specific address which is very handy. - -## Boot flow elements - -The following table lists the boot flow in order. - -Item | Notes ------|------- -[ARM Trusted Firmware (TF-A)](https://github.com/ARM-software/arm-trusted-firmware) | TF-A is a de-facto standard reference firmware implementation and proven in the field.
TF-A runs post power-on on Armv8-A implementations and eventually hands off to further stages of the boot flow.
For qemu's virt machine platform, it is essentially absent but I mean to rely on it heavily for silicon bring up hence mentioning it here. -[u-boot](https://www.denx.de/wiki/U-Boot) | u-boot will handle early console access, media access for fetching redox kernel images from non-volatile storage/misc disk subsystems/off the network.
u-boot supports loading EFI applications. If EFI support to AArch64 Redox is added in the future that should essentially work out of the box.
u-boot will load redox and FDT binary blobs into RAM and jump to the redox kernel. -Redox early-init stub | For AArch64, the redox kernel will contain an A64 assembly stub that will setup the MMU from scratch. This is akin to the [x86_64 redox bootloader](https://github.com/redox-os/bootloader/blob/master/x86_64/startup-x86_64.asm).
This stub sets up identity maps for MMU initialization, maps the kernel image itself as well as the device memory for the UART console. At present this stub shall be a part of the kernel itself for simplicity. -Redox kstart entry | The early init stub hands off here. kstart will then re-init the MMU more comprehensively. - -## Supported devices - -The following devices shall be supported. All necessary information specific to these devices will be provided to the redox kernel by the platform specific FDT binary blob. - -Device | Notes --------|------- -[Generic Interrupt Controller v2](https://developer.arm.com/products/architecture/a-profile/docs/ihi0048/b/arm-generic-interrupt-controller-architecture-version-20-architecture-specification) | The GIC is an Arm-v8A architectural element and is supported by all architecturally compliant processor implementations. GICv2 is supported by qemu's virt machine emulation and most subsequent GIC implementations are backward compatible to GICv2. -[Generic Timer](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500d/BGBBIJCB.html) | The Generic Timer Architecture is an Arm-v8A architectural element and is implemented by all compliant processor implementations. It is supported by qemu. -[PrimeCell UART PL011](http://infocenter.arm.com/help/topic/com.arm.doc.ddi0183f/DDI0183.pdf) | The PL011 UART is supported by qemu and most ARM systems. - -## Intended development sequence and status - -Item | Description | Status | Notes ------|-------|-----|----- -Redox AArch64 toolchain | Create an usable redox AArch64 toolchain specification | Done | Using this JSON spec in isolated tests produces valid AArch64 soft float code -Stubbed kernel image | Stub out AArch64 kernel support using the existing x86_64 arch code as a template
Modify redox kernel build glue and work iteratively to get a linkable (non-functional) image | Not done yet | -Boot flow | Create a self hosted u-boot -> redox kernel workflow
Should obtain the stubbed image from a local TFTP server, load it into RAM and jump to it | Not done yet | -GDB Debug flow | Create a debug workflow centered around qemu's GDB stub
This should allow connecting to qemu's GDB stub and debug u-boot/redox stub via a GDB client and single stepping through code | Not done yet | -Verify Redox entry | Verify that control reaches the redox kernel from u-boot | Not done yet | -AArch64 early init stub | Add support for raw asm code for early AArch64 init in the redox kernel
Verify that this code is located appropriately in the link map and that control reaches this code from u-boot | Not done yet | -Basic DTB support | Integrate the [device_tree crate](https://mbr.github.io/device_tree-rs/device_tree/)
Use the crate to access the qemu supplied DTB image and extract the memory map | Not done yet | -Basic UART support | Use the device_tree crate to get the UART address from the DTB image and set up the initial console
This is a polling mode only setup | Not done yet | -Initial MMU support | Implement initial MMU support in the early init stub
This forces the MMU into a clean state overriding any bootloader specific setup
Create an identity map for MMU init
Create a mapping for the kernel image
Create a mapping for any devices needed at this stage (UART)| Not done yet | -kmain entry | Verify that kmain entry works post early MMU init | Not done yet | -Basic Redox MMU support | Get Redox to create a final set of mappings for everything
Verify that this works as expected| Not done yet | -Basic libc support | Flesh out a basic set of libc calls as required for simple user-land apps | Not done yet | -userspace_init entry | Verify user-space entry and /sbin/init invocation | Not done yet | -Basic Interrupt controller support | Add a GIC driver
Verify functionality | Not done yet | -Basic Timer support | Add a Generic Timer driver
Verify functionality | Not done yet | -UART interrupt support | Add support for UART interrupts | Not done yet | -Task context switch support | Add context switching support
Verify functionality | Not done yet | -Login shell | Iteratively add and verify multi-user login shell support | Not done yet | -Publish development branch on github | Work with the community to post work done after employer approval | Not done yet | -Break out the Bubbly | Drink copious quantities of alcohol to celebrate | Not done yet | -Silicon bring-up | Plan silicon bring-up | Not done yet | +# Porting the core Redox kernel to arm AArch64: An outline + +## Intro + +This document is [my](https://github.com/raw-bin) attempt at: + +* Capturing thinking on the work needed for a core Redox kernel port +* Sharing progress with the community as things evolve +* Creating a template that can be used for ports to other architectures + +Core Redox kernel means everything needed to get to a non-graphical console-only multi-user shell. + +Only the 64-bit execution state (AArch64) with the 64-bit instruction set architecture (A64) shall be supported for the moment. For more background/context read [this](https://developer.arm.com/products/architecture/a-profile/docs/den0024/latest/introduction). + +This document is intended to be kept *live*. It will be updated to reflect the current state of work and any feedback received. + +It is hard~futile to come up with a strict sequence of work for such ports but this document is a reasonable template to follow. + +## Intended target platform + +The primary focus is on [qemu's virt machine platform emulation for the AArch64 architecture](https://github.com/qemu/qemu/blob/master/hw/arm/virt.c#L127). + +Targeting a virtual platform is a convenient way to bring up the mechanics of architectural support and makes the jump to silicon easier. The preferred boot chain for AArch64 (explained later) is well supported on this platform and boot-over-tftp from localhost makes the debug cycle very efficient. + +Once the core kernel port is complete a similar follow on document will be created that is dedicated to silicon bring-up. + +## Boot protocol elements + +Item | Notes +-----|------- +[Linux kernel boot protocol for AArch64](https://www.kernel.org/doc/Documentation/arm64/booting.txt) | The linked document describes assumptions made from the bootloader which are field tested and worthwhile to have for Redox an AArch64.
The intent is to consider most of the document except anything tied to the Linux kernel itself. +[Flattened Device Tree](https://elinux.org/Device_Tree_Reference) | FDT binary blobs supplied by the bootloader shall provide the Redox kernel with misc platform \{memory, interrupt, devicemem} maps. Qemu's virt machine platform synthetically creates an FDT blob at a specific address which is very handy. + +## Boot flow elements + +The following table lists the boot flow in order. + +Item | Notes +-----|------- +[ARM Trusted Firmware (TF-A)](https://github.com/ARM-software/arm-trusted-firmware) | TF-A is a de-facto standard reference firmware implementation and proven in the field.
TF-A runs post power-on on Armv8-A implementations and eventually hands off to further stages of the boot flow.
For qemu's virt machine platform, it is essentially absent but I mean to rely on it heavily for silicon bring up hence mentioning it here. +[u-boot](https://www.denx.de/wiki/U-Boot) | u-boot will handle early console access, media access for fetching redox kernel images from non-volatile storage/misc disk subsystems/off the network.
u-boot supports loading EFI applications. If EFI support to AArch64 Redox is added in the future that should essentially work out of the box.
u-boot will load redox and FDT binary blobs into RAM and jump to the redox kernel. +Redox early-init stub | For AArch64, the redox kernel will contain an A64 assembly stub that will setup the MMU from scratch. This is akin to the [x86_64 redox bootloader](https://github.com/redox-os/bootloader/blob/master/x86_64/startup-x86_64.asm).
This stub sets up identity maps for MMU initialization, maps the kernel image itself as well as the device memory for the UART console. At present this stub shall be a part of the kernel itself for simplicity. +Redox kstart entry | The early init stub hands off here. kstart will then re-init the MMU more comprehensively. + +## Supported devices + +The following devices shall be supported. All necessary information specific to these devices will be provided to the redox kernel by the platform specific FDT binary blob. + +Device | Notes +-------|------- +[Generic Interrupt Controller v2](https://developer.arm.com/products/architecture/a-profile/docs/ihi0048/b/arm-generic-interrupt-controller-architecture-version-20-architecture-specification) | The GIC is an Arm-v8A architectural element and is supported by all architecturally compliant processor implementations. GICv2 is supported by qemu's virt machine emulation and most subsequent GIC implementations are backward compatible to GICv2. +[Generic Timer](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500d/BGBBIJCB.html) | The Generic Timer Architecture is an Arm-v8A architectural element and is implemented by all compliant processor implementations. It is supported by qemu. +[PrimeCell UART PL011](http://infocenter.arm.com/help/topic/com.arm.doc.ddi0183f/DDI0183.pdf) | The PL011 UART is supported by qemu and most ARM systems. + +## Intended development sequence and status + +Item | Description | Status | Notes +-----|-------|-----|----- +Redox AArch64 toolchain | Create an usable redox AArch64 toolchain specification | Done | Using this JSON spec in isolated tests produces valid AArch64 soft float code +Stubbed kernel image | Stub out AArch64 kernel support using the existing x86_64 arch code as a template
Modify redox kernel build glue and work iteratively to get a linkable (non-functional) image | Not done yet | +Boot flow | Create a self hosted u-boot -> redox kernel workflow
Should obtain the stubbed image from a local TFTP server, load it into RAM and jump to it | Not done yet | +GDB Debug flow | Create a debug workflow centered around qemu's GDB stub
This should allow connecting to qemu's GDB stub and debug u-boot/redox stub via a GDB client and single stepping through code | Not done yet | +Verify Redox entry | Verify that control reaches the redox kernel from u-boot | Not done yet | +AArch64 early init stub | Add support for raw asm code for early AArch64 init in the redox kernel
Verify that this code is located appropriately in the link map and that control reaches this code from u-boot | Not done yet | +Basic DTB support | Integrate the [device_tree crate](https://mbr.github.io/device_tree-rs/device_tree/)
Use the crate to access the qemu supplied DTB image and extract the memory map | Not done yet | +Basic UART support | Use the device_tree crate to get the UART address from the DTB image and set up the initial console
This is a polling mode only setup | Not done yet | +Initial MMU support | Implement initial MMU support in the early init stub
This forces the MMU into a clean state overriding any bootloader specific setup
Create an identity map for MMU init
Create a mapping for the kernel image
Create a mapping for any devices needed at this stage (UART)| Not done yet | +kmain entry | Verify that kmain entry works post early MMU init | Not done yet | +Basic Redox MMU support | Get Redox to create a final set of mappings for everything
Verify that this works as expected| Not done yet | +Basic libc support | Flesh out a basic set of libc calls as required for simple user-land apps | Not done yet | +userspace_init entry | Verify user-space entry and /sbin/init invocation | Not done yet | +Basic Interrupt controller support | Add a GIC driver
Verify functionality | Not done yet | +Basic Timer support | Add a Generic Timer driver
Verify functionality | Not done yet | +UART interrupt support | Add support for UART interrupts | Not done yet | +Task context switch support | Add context switching support
Verify functionality | Not done yet | +Login shell | Iteratively add and verify multi-user login shell support | Not done yet | +Publish development branch on github | Work with the community to post work done after employer approval | Not done yet | +Break out the Bubbly | Drink copious quantities of alcohol to celebrate | Not done yet | +Silicon bring-up | Plan silicon bring-up | Not done yet | diff --git a/Cargo.lock b/Cargo.lock index 6901c00bf..9543feb8c 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1,502 +1,1005 @@ -# This file is automatically @generated by Cargo. -# It is not intended for manual editing. -version = 4 - -[[package]] -name = "ahash" -version = "0.8.11" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e89da841a80418a9b391ebaea17f5c112ffaaa96f621d2c285b5174da76b9011" -dependencies = [ - "cfg-if", - "once_cell", - "version_check", - "zerocopy", -] - -[[package]] -name = "arrayvec" -version = "0.7.6" -source = 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-[package] -name = "kernel" -version = "0.5.12" -build = "build.rs" -edition = "2021" - -[build-dependencies] -cc = "1.0" -rustc-cfg = "0.5" -toml = "0.8" - -[dependencies] -bitflags = "2" -bitfield = "0.13.2" -hashbrown = { version = "0.14.3", default-features = false, features = ["ahash", "inline-more"] } -linked_list_allocator = "0.9.0" -log = "0.4" -redox-path = "0.2.0" -redox_syscall = { git = "https://gitlab.redox-os.org/redox-os/syscall.git", branch = "master", default-features = false } -slab_allocator = { path = "slab_allocator", optional = true } -spin = "0.9.8" -spinning_top = { version = "0.3", features = ["arc_lock"] } -rmm = { path = "rmm", default-features = false } -arrayvec = { version = "0.7.4", default-features = false } -slab = { version = "0.4", default-features = false } -# TODO: Remove -indexmap = { version = "2.5.0", default-features = false } - -[dependencies.goblin] -version = "0.2.1" -default-features = false -features = ["elf32", "elf64"] - -[dependencies.rustc-demangle] -version = "0.1.16" -default-features = false - -[target.'cfg(any(target_arch = "aarch64", target_arch = "riscv64"))'.dependencies] -byteorder = { version = "1", default-features = false } -fdt = { git = "https://github.com/repnop/fdt.git", rev = "2fb1409edd1877c714a0aa36b6a7c5351004be54" } - -[target.'cfg(any(target_arch = "x86", target_arch = "x86_64"))'.dependencies] -raw-cpuid = "10.2.0" -x86 = { version = "0.47.0", default-features = false } - -[target.'cfg(any(target_arch = "riscv64", target_arch = "riscv32"))'.dependencies] -sbi-rt = "0.0.3" - -[features] -default = [ - "acpi", - #TODO: issues with Alder Lake and newer CPUs: "multi_core", - # This may be because of mismatch between cpu id and apic id - "graphical_debug", - "serial_debug", - "self_modifying", - "x86_kvm_pv", - #"syscall_debug" -] - -# Activates some limited code-overwriting optimizations, based on CPU features. -self_modifying = [] - -acpi = [] -graphical_debug = [] -lpss_debug = [] -multi_core = ["acpi"] -profiling = [] -#TODO: remove when threading issues are fixed -pti = [] -qemu_debug = [] -serial_debug = [] -system76_ec_debug = [] -slab = ["slab_allocator"] -sys_stat = [] -x86_kvm_pv = [] - -debugger = ["syscall_debug"] -syscall_debug = [] - -sys_fdstat = [] - -[profile.dev] -# Avoids having to define the eh_personality lang item and reduces kernel size -panic = "abort" - -[profile.release] -# Avoids having to define the eh_personality lang item and reduces kernel size -panic = "abort" - -#lto = true - -debug = "full" +[package] +name = "kernel" +version = "0.5.12" +build = "build.rs" +edition = "2021" + +[build-dependencies] +cc = "1.0" +rustc-cfg = "0.5" +toml = "0.8" + +[dependencies] +bitflags = "2" +bitfield = "0.13.2" +hashbrown = { version = "0.14.3", default-features = false, features = ["ahash", "inline-more"] } +linked_list_allocator = "0.9.0" +log = "0.4" +redox-path = "0.2.0" +redox_syscall = { git = "https://gitlab.redox-os.org/redox-os/syscall.git", branch = "master", default-features = false } +slab_allocator = { path = "slab_allocator", optional = true } +spin = "0.9.8" +spinning_top = { version = "0.3", features = ["arc_lock"] } +rmm = { path = "rmm", default-features = false } +arrayvec = { version = "0.7.4", default-features = false } +slab = { version = "0.4", default-features = false } +# TODO: Remove +indexmap = { version = "2.5.0", default-features = false } + +[dependencies.goblin] +version = "0.2.1" +default-features = false +features = ["elf32", "elf64"] + +[dependencies.rustc-demangle] +version = "0.1.16" +default-features = false + +[target.'cfg(any(target_arch = "aarch64", target_arch = "riscv64"))'.dependencies] +byteorder = { version = "1", default-features = false } +fdt = { git = "https://github.com/repnop/fdt.git", rev = "2fb1409edd1877c714a0aa36b6a7c5351004be54" } + +[target.'cfg(any(target_arch = "x86", target_arch = "x86_64"))'.dependencies] +raw-cpuid = "10.2.0" +x86 = { version = "0.47.0", default-features = false } + +[target.'cfg(any(target_arch = "riscv64", target_arch = "riscv32"))'.dependencies] +sbi-rt = "0.0.3" + +[features] +default = [ + "acpi", + # TODO: Re-enable after comprehensive testing of hybrid CPU topology fixes + # Previous issues with Alder Lake+ CPUs due to APIC ID vs CPU ID mismatch + # should now be better handled with extended topology detection (CPUID 1F/0B) + # and proper P-core/E-core identification. Enable cautiously for testing. + #"multi_core", + "graphical_debug", + "serial_debug", + "self_modifying", + "x86_kvm_pv", + #"syscall_debug" +] + +# Activates some limited code-overwriting optimizations, based on CPU features. +self_modifying = [] + +acpi = [] +graphical_debug = [] +lpss_debug = [] +multi_core = ["acpi"] +profiling = [] +#TODO: remove when threading issues are fixed +pti = [] +qemu_debug = [] +serial_debug = [] +system76_ec_debug = [] +slab = ["slab_allocator"] +sys_stat = [] +x86_kvm_pv = [] + +debugger = ["syscall_debug"] +syscall_debug = [] + +sys_fdstat = [] + +[profile.dev] +# Avoids having to define the eh_personality lang item and reduces kernel size +panic = "abort" + +[profile.release] +# Avoids having to define the eh_personality lang item and reduces kernel size +panic = "abort" + +#lto = true + +debug = "full" diff --git a/LICENSE b/LICENSE index eeb7504cd..2386159ea 100644 --- a/LICENSE +++ b/LICENSE @@ -1,21 +1,21 @@ -MIT License - -Copyright (c) 2017 Jeremy Soller - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. +MIT License + +Copyright (c) 2017 Jeremy Soller + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/Makefile b/Makefile index 5703ee2f9..8058213e7 100644 --- a/Makefile +++ b/Makefile @@ -1,44 +1,44 @@ -SOURCE:=$(dir $(realpath $(lastword $(MAKEFILE_LIST)))) -BUILD?=$(CURDIR) -export RUST_TARGET_PATH=$(SOURCE)/targets - -ifeq ($(TARGET),) - ARCH?=$(shell uname -m) -else - ARCH?=$(shell echo "$(TARGET)" | cut -d - -f1) -endif - -ifeq ($(ARCH),riscv64gc) - override ARCH:=riscv64 -endif -GNU_TARGET=$(ARCH)-unknown-redox - - -all: $(BUILD)/kernel $(BUILD)/kernel.sym - -LD_SCRIPT=$(SOURCE)/linkers/$(ARCH).ld -TARGET_SPEC=$(RUST_TARGET_PATH)/$(ARCH)-unknown-kernel.json - -$(BUILD)/kernel.all: $(LD_SCRIPT) $(TARGET_SPEC) $(shell find $(SOURCE) -name "*.rs" -type f) - cargo rustc \ - --bin kernel \ - --manifest-path "$(SOURCE)/Cargo.toml" \ - --target "$(TARGET_SPEC)" \ - --release \ - -Z build-std=core,alloc \ - -- \ - -C link-arg=-T -Clink-arg="$(LD_SCRIPT)" \ - -C link-arg=-z -Clink-arg=max-page-size=0x1000 \ - --emit link="$(BUILD)/kernel.all" - -$(BUILD)/kernel.sym: $(BUILD)/kernel.all - $(GNU_TARGET)-objcopy \ - --only-keep-debug \ - "$(BUILD)/kernel.all" \ - "$(BUILD)/kernel.sym" - -$(BUILD)/kernel: $(BUILD)/kernel.all - $(GNU_TARGET)-objcopy \ - --strip-debug \ - "$(BUILD)/kernel.all" \ - "$(BUILD)/kernel" +SOURCE:=$(dir $(realpath $(lastword $(MAKEFILE_LIST)))) +BUILD?=$(CURDIR) +export RUST_TARGET_PATH=$(SOURCE)/targets + +ifeq ($(TARGET),) + ARCH?=$(shell uname -m) +else + ARCH?=$(shell echo "$(TARGET)" | cut -d - -f1) +endif + +ifeq ($(ARCH),riscv64gc) + override ARCH:=riscv64 +endif +GNU_TARGET=$(ARCH)-unknown-redox + + +all: $(BUILD)/kernel $(BUILD)/kernel.sym + +LD_SCRIPT=$(SOURCE)/linkers/$(ARCH).ld +TARGET_SPEC=$(RUST_TARGET_PATH)/$(ARCH)-unknown-kernel.json + +$(BUILD)/kernel.all: $(LD_SCRIPT) $(TARGET_SPEC) $(shell find $(SOURCE) -name "*.rs" -type f) + cargo rustc \ + --bin kernel \ + --manifest-path "$(SOURCE)/Cargo.toml" \ + --target "$(TARGET_SPEC)" \ + --release \ + -Z build-std=core,alloc \ + -- \ + -C link-arg=-T -Clink-arg="$(LD_SCRIPT)" \ + -C link-arg=-z -Clink-arg=max-page-size=0x1000 \ + --emit link="$(BUILD)/kernel.all" + +$(BUILD)/kernel.sym: $(BUILD)/kernel.all + $(GNU_TARGET)-objcopy \ + --only-keep-debug \ + "$(BUILD)/kernel.all" \ + "$(BUILD)/kernel.sym" + +$(BUILD)/kernel: $(BUILD)/kernel.all + $(GNU_TARGET)-objcopy \ + --strip-debug \ + "$(BUILD)/kernel.all" \ + "$(BUILD)/kernel" diff --git a/README.md b/README.md index cf54d099e..2a4428f77 100644 --- a/README.md +++ b/README.md @@ -1,81 +1,81 @@ -# Kernel - -Redox OS Microkernel - -[![docs](https://img.shields.io/badge/docs-master-blue.svg)](https://docs.rs/redox_syscall/latest/syscall/) -[![SLOCs counter](https://tokei.rs/b1/github/redox-os/kernel?category=code)](https://github.com/XAMPPRocky/tokei) -[![MIT licensed](https://img.shields.io/badge/license-MIT-blue.svg)](./LICENSE) - -## Requirements - -* [`nasm`](https://nasm.us/) needs to be available on the PATH at build time. - -## Building The Documentation - -Use this command: - -```sh -cargo doc --open --target x86_64-unknown-none -``` - -## Debugging - -### QEMU - -Running [QEMU](https://www.qemu.org) with the `-s` flag will set up QEMU to listen on port `1234` for a GDB client to connect to it. To debug the redox kernel run. - -```sh -make qemu gdb=yes -``` - -This will start a virtual machine with and listen on port `1234` for a GDB or LLDB client. - -### GDB - -If you are going to use [GDB](https://www.gnu.org/software/gdb/), run these commands to load debug symbols and connect to your running kernel: - -``` -(gdb) symbol-file build/kernel.sym -(gdb) target remote localhost:1234 -``` - -### LLDB - -If you are going to use [LLDB](https://lldb.llvm.org/), run these commands to start debugging: - -``` -(lldb) target create -s build/kernel.sym build/kernel -(lldb) gdb-remote localhost:1234 -``` - -After connecting to your kernel you can set some interesting breakpoints and `continue` -the process. See your debuggers man page for more information on useful commands to run. - -## Notes - -- Always use `foo.get(n)` instead of `foo[n]` and try to cover for the possibility of `Option::None`. Doing the regular way may work fine for applications, but never in the kernel. No possible panics should ever exist in kernel space, because then the whole OS would just stop working. - -- If you receive a kernel panic in QEMU, use `pkill qemu-system` to kill the frozen QEMU process. - -## How To Contribute - -To learn how to contribute to this system component you need to read the following document: - -- [CONTRIBUTING.md](https://gitlab.redox-os.org/redox-os/redox/-/blob/master/CONTRIBUTING.md) - -## Development - -To learn how to do development with this system component inside the Redox build system you need to read the [Build System](https://doc.redox-os.org/book/build-system-reference.html) and [Coding and Building](https://doc.redox-os.org/book/coding-and-building.html) pages. - -### How To Build - -To build this system component you need to download the Redox build system, you can learn how to do it on the [Building Redox](https://doc.redox-os.org/book/podman-build.html) page. - -This is necessary because they only work with cross-compilation to a Redox virtual machine, but you can do some testing from Linux. - -## Funding - _Unix-style Signals and Process Management_ - -This project is funded through [NGI Zero Core](https://nlnet.nl/core), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more at the [NLnet project page](https://nlnet.nl/project/RedoxOS-Signals). - -[NLnet foundation logo](https://nlnet.nl) -[NGI Zero Logo](https://nlnet.nl/core) +# Kernel + +Redox OS Microkernel + +[![docs](https://img.shields.io/badge/docs-master-blue.svg)](https://docs.rs/redox_syscall/latest/syscall/) +[![SLOCs counter](https://tokei.rs/b1/github/redox-os/kernel?category=code)](https://github.com/XAMPPRocky/tokei) +[![MIT licensed](https://img.shields.io/badge/license-MIT-blue.svg)](./LICENSE) + +## Requirements + +* [`nasm`](https://nasm.us/) needs to be available on the PATH at build time. + +## Building The Documentation + +Use this command: + +```sh +cargo doc --open --target x86_64-unknown-none +``` + +## Debugging + +### QEMU + +Running [QEMU](https://www.qemu.org) with the `-s` flag will set up QEMU to listen on port `1234` for a GDB client to connect to it. To debug the redox kernel run. + +```sh +make qemu gdb=yes +``` + +This will start a virtual machine with and listen on port `1234` for a GDB or LLDB client. + +### GDB + +If you are going to use [GDB](https://www.gnu.org/software/gdb/), run these commands to load debug symbols and connect to your running kernel: + +``` +(gdb) symbol-file build/kernel.sym +(gdb) target remote localhost:1234 +``` + +### LLDB + +If you are going to use [LLDB](https://lldb.llvm.org/), run these commands to start debugging: + +``` +(lldb) target create -s build/kernel.sym build/kernel +(lldb) gdb-remote localhost:1234 +``` + +After connecting to your kernel you can set some interesting breakpoints and `continue` +the process. See your debuggers man page for more information on useful commands to run. + +## Notes + +- Always use `foo.get(n)` instead of `foo[n]` and try to cover for the possibility of `Option::None`. Doing the regular way may work fine for applications, but never in the kernel. No possible panics should ever exist in kernel space, because then the whole OS would just stop working. + +- If you receive a kernel panic in QEMU, use `pkill qemu-system` to kill the frozen QEMU process. + +## How To Contribute + +To learn how to contribute to this system component you need to read the following document: + +- [CONTRIBUTING.md](https://gitlab.redox-os.org/redox-os/redox/-/blob/master/CONTRIBUTING.md) + +## Development + +To learn how to do development with this system component inside the Redox build system you need to read the [Build System](https://doc.redox-os.org/book/build-system-reference.html) and [Coding and Building](https://doc.redox-os.org/book/coding-and-building.html) pages. + +### How To Build + +To build this system component you need to download the Redox build system, you can learn how to do it on the [Building Redox](https://doc.redox-os.org/book/podman-build.html) page. + +This is necessary because they only work with cross-compilation to a Redox virtual machine, but you can do some testing from Linux. + +## Funding - _Unix-style Signals and Process Management_ + +This project is funded through [NGI Zero Core](https://nlnet.nl/core), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more at the [NLnet project page](https://nlnet.nl/project/RedoxOS-Signals). + +[NLnet foundation logo](https://nlnet.nl) +[NGI Zero Logo](https://nlnet.nl/core) diff --git a/clippy.sh b/clippy.sh index 655f1b893..9b937b65c 100755 --- a/clippy.sh +++ b/clippy.sh @@ -1,7 +1,7 @@ -#!/usr/bin/env bash - -set -e - -export RUST_TARGET_PATH="${PWD}/targets" -export RUSTFLAGS="-C soft-float -C debuginfo=2" -cargo clippy --lib --release --target x86_64-unknown-none "$@" +#!/usr/bin/env bash + +set -e + +export RUST_TARGET_PATH="${PWD}/targets" +export RUSTFLAGS="-C soft-float -C debuginfo=2" +cargo clippy --lib --release --target x86_64-unknown-none "$@" diff --git a/config.toml.example b/config.toml.example index b3cdb9e7f..c79841e15 100644 --- a/config.toml.example +++ b/config.toml.example @@ -1,7 +1,7 @@ -[arch.x86_64.features] -smap = "auto" -fsgsbase = "auto" -xsave = "auto" -xsaveopt = "auto" - -# vim: ft=toml +[arch.x86_64.features] +smap = "auto" +fsgsbase = "auto" +xsave = "auto" +xsaveopt = "auto" + +# vim: ft=toml diff --git a/linkers/aarch64.ld b/linkers/aarch64.ld index f679c9af3..303223eba 100644 --- a/linkers/aarch64.ld +++ b/linkers/aarch64.ld @@ -1,62 +1,62 @@ -ENTRY(kstart) -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") - -KERNEL_OFFSET = 0xFFFFFF0000000000; - -SECTIONS { - . = KERNEL_OFFSET; - - . += SIZEOF_HEADERS; - - /* Force the zero page to be part of a segment by creating a - * dummy section in the zero page. - * Limine will map the segment with the lowest vaddr value at - * 0xFFFFFFFF80000000 even if the segment has a higher vaddr. - * As such without the zero page being part of a segment, the - * kernel would be loaded at an offset from the expected - * location. As the redox kernel is not currently relocatable, - * this would result in a crash. A similar issue likely exists - * with multiboot/multiboot2 and the paddr of the segment. - */ - .dummy ALIGN(8) : AT(ADDR(.dummy) - KERNEL_OFFSET) {} - - . = ALIGN(4096); - - .text : AT(ADDR(.text) - KERNEL_OFFSET) { - __text_start = .; - *(.text*) - __usercopy_start = .; - *(.usercopy-fns) - __usercopy_end = .; - . = ALIGN(4096); - __text_end = .; - } - - .rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) { - __rodata_start = .; - *(.rodata*) - . = ALIGN(4096); - __rodata_end = .; - } - - .data : AT(ADDR(.data) - KERNEL_OFFSET) { - __data_start = .; - *(.data*) - . = ALIGN(4096); - __data_end = .; - __bss_start = .; - *(.bss*) - . = ALIGN(4096); - __bss_end = .; - } - - __end = .; - - /DISCARD/ : { - *(.comment*) - *(.eh_frame*) - *(.gcc_except_table*) - *(.note*) - *(.rel.eh_frame*) - } -} +ENTRY(kstart) +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") + +KERNEL_OFFSET = 0xFFFFFF0000000000; + +SECTIONS { + . = KERNEL_OFFSET; + + . += SIZEOF_HEADERS; + + /* Force the zero page to be part of a segment by creating a + * dummy section in the zero page. + * Limine will map the segment with the lowest vaddr value at + * 0xFFFFFFFF80000000 even if the segment has a higher vaddr. + * As such without the zero page being part of a segment, the + * kernel would be loaded at an offset from the expected + * location. As the redox kernel is not currently relocatable, + * this would result in a crash. A similar issue likely exists + * with multiboot/multiboot2 and the paddr of the segment. + */ + .dummy ALIGN(8) : AT(ADDR(.dummy) - KERNEL_OFFSET) {} + + . = ALIGN(4096); + + .text : AT(ADDR(.text) - KERNEL_OFFSET) { + __text_start = .; + *(.text*) + __usercopy_start = .; + *(.usercopy-fns) + __usercopy_end = .; + . = ALIGN(4096); + __text_end = .; + } + + .rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) { + __rodata_start = .; + *(.rodata*) + . = ALIGN(4096); + __rodata_end = .; + } + + .data : AT(ADDR(.data) - KERNEL_OFFSET) { + __data_start = .; + *(.data*) + . = ALIGN(4096); + __data_end = .; + __bss_start = .; + *(.bss*) + . = ALIGN(4096); + __bss_end = .; + } + + __end = .; + + /DISCARD/ : { + *(.comment*) + *(.eh_frame*) + *(.gcc_except_table*) + *(.note*) + *(.rel.eh_frame*) + } +} diff --git a/linkers/i686.ld b/linkers/i686.ld index f7eb9c429..def4c2102 100644 --- a/linkers/i686.ld +++ b/linkers/i686.ld @@ -1,57 +1,57 @@ -ENTRY(kstart) -OUTPUT_FORMAT(elf32-i386) - -KERNEL_OFFSET = 0xC0000000; - -SECTIONS { - . = KERNEL_OFFSET; - - . += SIZEOF_HEADERS; - - /* Force the zero page to be part of a segment by creating a - * dummy section in the zero page. - * Limine will map the segment with the lowest vaddr value at - * 0xFFFFFFFF80000000 even if the segment has a higher vaddr. - * As such without the zero page being part of a segment, the - * kernel would be loaded at an offset from the expected - * location. As the redox kernel is not currently relocatable, - * this would result in a crash. A similar issue likely exists - * with multiboot/multiboot2 and the paddr of the segment. - */ - .dummy : AT(ADDR(.dummy) - KERNEL_OFFSET) {} - - .text ALIGN(4K) : AT(ADDR(.text) - KERNEL_OFFSET) { - __text_start = .; - *(.text*) - __usercopy_start = .; - *(.usercopy-fns) - __usercopy_end = .; - } - - .rodata ALIGN(4K) : AT(ADDR(.rodata) - KERNEL_OFFSET) { - __text_end = .; - __rodata_start = .; - *(.rodata*) - } - - .data ALIGN(4K) : AT(ADDR(.data) - KERNEL_OFFSET) { - __rodata_end = .; - __data_start = .; - *(.data*) - . = ALIGN(4K); - __data_end = .; - __bss_start = .; - *(.bss*) - . = ALIGN(4K); - } - - __end = .; - - /DISCARD/ : { - *(.comment*) - *(.eh_frame*) - *(.gcc_except_table*) - *(.note*) - *(.rel.eh_frame*) - } -} +ENTRY(kstart) +OUTPUT_FORMAT(elf32-i386) + +KERNEL_OFFSET = 0xC0000000; + +SECTIONS { + . = KERNEL_OFFSET; + + . += SIZEOF_HEADERS; + + /* Force the zero page to be part of a segment by creating a + * dummy section in the zero page. + * Limine will map the segment with the lowest vaddr value at + * 0xFFFFFFFF80000000 even if the segment has a higher vaddr. + * As such without the zero page being part of a segment, the + * kernel would be loaded at an offset from the expected + * location. As the redox kernel is not currently relocatable, + * this would result in a crash. A similar issue likely exists + * with multiboot/multiboot2 and the paddr of the segment. + */ + .dummy : AT(ADDR(.dummy) - KERNEL_OFFSET) {} + + .text ALIGN(4K) : AT(ADDR(.text) - KERNEL_OFFSET) { + __text_start = .; + *(.text*) + __usercopy_start = .; + *(.usercopy-fns) + __usercopy_end = .; + } + + .rodata ALIGN(4K) : AT(ADDR(.rodata) - KERNEL_OFFSET) { + __text_end = .; + __rodata_start = .; + *(.rodata*) + } + + .data ALIGN(4K) : AT(ADDR(.data) - KERNEL_OFFSET) { + __rodata_end = .; + __data_start = .; + *(.data*) + . = ALIGN(4K); + __data_end = .; + __bss_start = .; + *(.bss*) + . = ALIGN(4K); + } + + __end = .; + + /DISCARD/ : { + *(.comment*) + *(.eh_frame*) + *(.gcc_except_table*) + *(.note*) + *(.rel.eh_frame*) + } +} diff --git a/linkers/riscv64.ld b/linkers/riscv64.ld index 634b5c2ca..cd88e1c93 100644 --- a/linkers/riscv64.ld +++ b/linkers/riscv64.ld @@ -1,68 +1,68 @@ -ENTRY(kstart) -OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv" ) - -KERNEL_OFFSET = 0xFFFFFF0000000000; - -SECTIONS { - . = KERNEL_OFFSET; - - . += SIZEOF_HEADERS; - - /* Force the zero page to be part of a segment by creating a - * dummy section in the zero page. - * Linker will map the segment with the lowest vaddr value at - * 0xFFFFFF0000000000 even if the segment has a higher vaddr. - * As such without the zero page being part of a segment, the - * kernel would be loaded at an offset from the expected - * location. As the redox kernel is not currently relocatable, - * this would result in a crash. A similar issue likely exists - * with multiboot/multiboot2 and the paddr of the segment. - */ - .dummy ALIGN(8) : AT(ADDR(.dummy) - KERNEL_OFFSET) {} - - . = ALIGN(4096); - - .text : AT(ADDR(.text) - KERNEL_OFFSET) { - __text_start = .; - *(.early_init.text*) - . = ALIGN(4096); - *(.text*) - __usercopy_start = .; - *(.usercopy-fns) - __usercopy_end = .; - . = ALIGN(4096); - __text_end = .; - } - - .rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) { - __rodata_start = .; - *(.rodata*) - . = ALIGN(4096); - __rodata_end = .; - } - - .data : AT(ADDR(.data) - KERNEL_OFFSET) { - __data_start = .; - *(.data*) - *(.sdata*) - . = ALIGN(4096); - __data_end = .; - *(.got*) - . = ALIGN(4096); - __bss_start = .; - *(.bss*) - *(.sbss*) - . = ALIGN(4096); - __bss_end = .; - } - - __end = .; - - /DISCARD/ : { - *(.comment*) - *(.eh_frame*) - *(.gcc_except_table*) - *(.note*) - *(.rel.eh_frame*) - } -} +ENTRY(kstart) +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv" ) + +KERNEL_OFFSET = 0xFFFFFF0000000000; + +SECTIONS { + . = KERNEL_OFFSET; + + . += SIZEOF_HEADERS; + + /* Force the zero page to be part of a segment by creating a + * dummy section in the zero page. + * Linker will map the segment with the lowest vaddr value at + * 0xFFFFFF0000000000 even if the segment has a higher vaddr. + * As such without the zero page being part of a segment, the + * kernel would be loaded at an offset from the expected + * location. As the redox kernel is not currently relocatable, + * this would result in a crash. A similar issue likely exists + * with multiboot/multiboot2 and the paddr of the segment. + */ + .dummy ALIGN(8) : AT(ADDR(.dummy) - KERNEL_OFFSET) {} + + . = ALIGN(4096); + + .text : AT(ADDR(.text) - KERNEL_OFFSET) { + __text_start = .; + *(.early_init.text*) + . = ALIGN(4096); + *(.text*) + __usercopy_start = .; + *(.usercopy-fns) + __usercopy_end = .; + . = ALIGN(4096); + __text_end = .; + } + + .rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) { + __rodata_start = .; + *(.rodata*) + . = ALIGN(4096); + __rodata_end = .; + } + + .data : AT(ADDR(.data) - KERNEL_OFFSET) { + __data_start = .; + *(.data*) + *(.sdata*) + . = ALIGN(4096); + __data_end = .; + *(.got*) + . = ALIGN(4096); + __bss_start = .; + *(.bss*) + *(.sbss*) + . = ALIGN(4096); + __bss_end = .; + } + + __end = .; + + /DISCARD/ : { + *(.comment*) + *(.eh_frame*) + *(.gcc_except_table*) + *(.note*) + *(.rel.eh_frame*) + } +} diff --git a/linkers/x86_64.ld b/linkers/x86_64.ld index 6610509ae..495f18084 100644 --- a/linkers/x86_64.ld +++ b/linkers/x86_64.ld @@ -1,66 +1,66 @@ -ENTRY(kstart) -OUTPUT_FORMAT(elf64-x86-64) - -KERNEL_OFFSET = 0xFFFFFFFF80000000; - -SECTIONS { - . = KERNEL_OFFSET; - - . += SIZEOF_HEADERS; - - /* Force the zero page to be part of a segment by creating a - * dummy section in the zero page. - * Limine will map the segment with the lowest vaddr value at - * 0xFFFFFFFF80000000 even if the segment has a higher vaddr. - * As such without the zero page being part of a segment, the - * kernel would be loaded at an offset from the expected - * location. As the redox kernel is not currently relocatable, - * this would result in a crash. A similar issue likely exists - * with multiboot/multiboot2 and the paddr of the segment. - */ - .dummy : AT(ADDR(.dummy) - KERNEL_OFFSET) {} - - .text ALIGN(4K) : AT(ADDR(.text) - KERNEL_OFFSET) { - __text_start = .; - *(.text*) - __usercopy_start = .; - *(.usercopy-fns) - __usercopy_end = .; - } - - .rodata ALIGN(4K) : AT(ADDR(.rodata) - KERNEL_OFFSET) { - __text_end = .; - __rodata_start = .; - *(.rodata*) - __altcode_start = .; - KEEP(*(.altcode*)) - __altcode_end = .; - . = ALIGN(8); - __altrelocs_start = .; - KEEP(*(.altrelocs*)) - __altrelocs_end = .; - __altfeatures_start = .; - KEEP(*(.altfeatures*)) - __altfeatures_end = .; - } - - .data ALIGN(4K) : AT(ADDR(.data) - KERNEL_OFFSET) { - __rodata_end = .; - __data_start = .; - *(.data*) - . = ALIGN(4K); - __data_end = .; - __bss_start = .; - *(.bss*) - } - - __end = .; - - /DISCARD/ : { - *(.comment*) - *(.eh_frame*) - *(.gcc_except_table*) - *(.note*) - *(.rel.eh_frame*) - } -} +ENTRY(kstart) +OUTPUT_FORMAT(elf64-x86-64) + +KERNEL_OFFSET = 0xFFFFFFFF80000000; + +SECTIONS { + . = KERNEL_OFFSET; + + . += SIZEOF_HEADERS; + + /* Force the zero page to be part of a segment by creating a + * dummy section in the zero page. + * Limine will map the segment with the lowest vaddr value at + * 0xFFFFFFFF80000000 even if the segment has a higher vaddr. + * As such without the zero page being part of a segment, the + * kernel would be loaded at an offset from the expected + * location. As the redox kernel is not currently relocatable, + * this would result in a crash. A similar issue likely exists + * with multiboot/multiboot2 and the paddr of the segment. + */ + .dummy : AT(ADDR(.dummy) - KERNEL_OFFSET) {} + + .text ALIGN(4K) : AT(ADDR(.text) - KERNEL_OFFSET) { + __text_start = .; + *(.text*) + __usercopy_start = .; + *(.usercopy-fns) + __usercopy_end = .; + } + + .rodata ALIGN(4K) : AT(ADDR(.rodata) - KERNEL_OFFSET) { + __text_end = .; + __rodata_start = .; + *(.rodata*) + __altcode_start = .; + KEEP(*(.altcode*)) + __altcode_end = .; + . = ALIGN(8); + __altrelocs_start = .; + KEEP(*(.altrelocs*)) + __altrelocs_end = .; + __altfeatures_start = .; + KEEP(*(.altfeatures*)) + __altfeatures_end = .; + } + + .data ALIGN(4K) : AT(ADDR(.data) - KERNEL_OFFSET) { + __rodata_end = .; + __data_start = .; + *(.data*) + . = ALIGN(4K); + __data_end = .; + __bss_start = .; + *(.bss*) + } + + __end = .; + + /DISCARD/ : { + *(.comment*) + *(.eh_frame*) + *(.gcc_except_table*) + *(.note*) + *(.rel.eh_frame*) + } +} diff --git a/rustfmt.toml b/rustfmt.toml index becbe9e6e..eda5d8844 100644 --- a/rustfmt.toml +++ b/rustfmt.toml @@ -1,21 +1,21 @@ -blank_lines_lower_bound = 0 # default -blank_lines_upper_bound = 1 # default -brace_style = "SameLineWhere" # default -disable_all_formatting = false # default -edition = "2021" -empty_item_single_line = true # default -fn_single_line = false # default -force_explicit_abi = true # default -format_strings = false # default -hard_tabs = false # default -show_parse_errors = true # default -imports_granularity = "Crate" # default = Preserve -imports_indent = "Block" # default -imports_layout = "Mixed" # default -indent_style = "Block" # default -max_width = 100 # default -newline_style = "Unix" # default = Auto -skip_children = false # default -tab_spaces = 4 # default -trailing_comma = "Vertical" # default -where_single_line = false # default +blank_lines_lower_bound = 0 # default +blank_lines_upper_bound = 1 # default +brace_style = "SameLineWhere" # default +disable_all_formatting = false # default +edition = "2021" +empty_item_single_line = true # default +fn_single_line = false # default +force_explicit_abi = true # default +format_strings = false # default +hard_tabs = false # default +show_parse_errors = true # default +imports_granularity = "Crate" # default = Preserve +imports_indent = "Block" # default +imports_layout = "Mixed" # default +indent_style = "Block" # default +max_width = 100 # default +newline_style = "Unix" # default = Auto +skip_children = false # default +tab_spaces = 4 # default +trailing_comma = "Vertical" # default +where_single_line = false # default diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs index a8121c687..df65cb20c 100644 --- a/src/acpi/madt/arch/x86.rs +++ b/src/acpi/madt/arch/x86.rs @@ -23,6 +23,15 @@ pub(super) fn init(madt: Madt) { println!(" XAPIC {}: {:>08X}", me, local_apic.address); } + // Validate APIC ID consistency with detected topology + let current_apic_id = local_apic.id(); + if !crate::cpu_topology::validate_acpi_apic_id(current_apic_id) { + log::warn!( + "BSP APIC ID {} from MADT doesn't match detected topology", + current_apic_id + ); + } + if cfg!(feature = "multi_core") { // Map trampoline let trampoline_frame = Frame::containing(PhysicalAddress::new(TRAMPOLINE)); @@ -57,6 +66,15 @@ pub(super) fn init(madt: Madt) { println!(" This is my local APIC"); } else { if ap_local_apic.flags & 1 == 1 { + // Validate APIC ID against detected topology + if !crate::cpu_topology::validate_acpi_apic_id(ap_local_apic.id.into()) + { + log::warn!( + "AP APIC ID {} from MADT not found in detected topology - may cause issues on hybrid CPUs", + ap_local_apic.id + ); + } + // Increase CPU ID CPU_COUNT.fetch_add(1, Ordering::SeqCst); diff --git a/src/arch/riscv64/device/irqchip/clint.rs b/src/arch/riscv64/device/irqchip/clint.rs index 560d86df0..b8afd66d7 100644 --- a/src/arch/riscv64/device/irqchip/clint.rs +++ b/src/arch/riscv64/device/irqchip/clint.rs @@ -1,42 +1,42 @@ -use spin::Mutex; -use syscall::{Io, Mmio}; -use crate::context::switch::tick; - -#[repr(packed(4))] -#[repr(C)] -struct ClintRegs { - /// per-hart MSIP registers - /// bit 0: trigger IPI for the hart - msip: [Mmio; 4095], // +0000 -- 3fff - _rsrv1: u32, - /// per-hart MTIMECMP registers - /// timer interrupt trigger threshold - mtimecmp: [Mmio; 4095], // +4000 - bff7 - mtime: Mmio // current time -} - -pub struct Clint { - regs: &'static mut ClintRegs, - freq: u64 -} - -pub static CLINT: Mutex> = Mutex::new(None); - -impl Clint { - pub fn new(addr: *mut u8, size: usize, freq: usize) -> Self { - assert!(size >= core::mem::size_of::()); - Self { - regs: unsafe { (addr as *mut ClintRegs).as_mut().unwrap() }, - freq: freq as u64 - } - } - - pub fn init(self: &mut Self) { - (*self.regs).mtimecmp[0].write((*self.regs).mtime.read() + self.freq / 100); - } - - pub fn timer_irq(self: &mut Self, hart: usize) { - (*self.regs).mtimecmp[hart].write((*self.regs).mtimecmp[hart].read() + self.freq / 100); - tick(); - } -} +use spin::Mutex; +use syscall::{Io, Mmio}; +use crate::context::switch::tick; + +#[repr(packed(4))] +#[repr(C)] +struct ClintRegs { + /// per-hart MSIP registers + /// bit 0: trigger IPI for the hart + msip: [Mmio; 4095], // +0000 -- 3fff + _rsrv1: u32, + /// per-hart MTIMECMP registers + /// timer interrupt trigger threshold + mtimecmp: [Mmio; 4095], // +4000 - bff7 + mtime: Mmio // current time +} + +pub struct Clint { + regs: &'static mut ClintRegs, + freq: u64 +} + +pub static CLINT: Mutex> = Mutex::new(None); + +impl Clint { + pub fn new(addr: *mut u8, size: usize, freq: usize) -> Self { + assert!(size >= core::mem::size_of::()); + Self { + regs: unsafe { (addr as *mut ClintRegs).as_mut().unwrap() }, + freq: freq as u64 + } + } + + pub fn init(self: &mut Self) { + (*self.regs).mtimecmp[0].write((*self.regs).mtime.read() + self.freq / 100); + } + + pub fn timer_irq(self: &mut Self, hart: usize) { + (*self.regs).mtimecmp[hart].write((*self.regs).mtimecmp[hart].read() + self.freq / 100); + tick(); + } +} diff --git a/src/arch/x86_shared/mod.rs b/src/arch/x86_shared/mod.rs index 21b6a208f..a0f0a9afc 100644 --- a/src/arch/x86_shared/mod.rs +++ b/src/arch/x86_shared/mod.rs @@ -33,6 +33,9 @@ pub mod stop; pub mod time; +/// CPU topology detection for modern hybrid architectures +pub mod topology; + #[cfg(target_arch = "x86")] pub use ::rmm::X86Arch as CurrentRmmArch; diff --git a/src/arch/x86_shared/topology.rs b/src/arch/x86_shared/topology.rs new file mode 100644 index 000000000..dd875517c --- /dev/null +++ b/src/arch/x86_shared/topology.rs @@ -0,0 +1,173 @@ +/// Extended CPU topology detection for modern Intel CPUs (Alder Lake+) +/// +/// This module implements proper APIC ID to logical CPU ID mapping for hybrid +/// architectures with P-cores and E-cores that break traditional sequential mapping. +use crate::arch::x86_shared::cpuid::cpuid; +use alloc::vec::Vec; +use core::fmt; + +/// Information about CPU topology and core types +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct CpuTopologyInfo { + /// Logical CPU ID used by the kernel + pub logical_id: u32, + /// Hardware APIC ID + pub apic_id: u32, + /// Type of CPU core (P-core vs E-core) + pub core_type: CoreType, + /// SMT thread ID within the core + pub smt_id: u32, + /// Core ID within the package + pub core_id: u32, + /// Package (socket) ID + pub package_id: u32, +} + +/// CPU core type for hybrid architectures +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum CoreType { + /// Performance core (Golden Cove on Alder Lake) + Performance, + /// Efficiency core (Gracemont on Alder Lake) + Efficiency, + /// Unknown or traditional core type + Unknown, +} + +impl fmt::Display for CoreType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + CoreType::Performance => write!(f, "P-core"), + CoreType::Efficiency => write!(f, "E-core"), + CoreType::Unknown => write!(f, "Unknown"), + } + } +} + +/// Extended topology detection result +#[derive(Debug)] +pub struct TopologyMap { + /// Mapping from logical CPU ID to topology info + pub cpus: Vec, + /// Whether this is a hybrid architecture (P-cores + E-cores) + pub is_hybrid: bool, + /// Maximum APIC ID found + pub max_apic_id: u32, +} + +impl TopologyMap { + /// Find topology info by logical CPU ID + pub fn get_by_logical_id(&self, logical_id: u32) -> Option<&CpuTopologyInfo> { + self.cpus.iter().find(|cpu| cpu.logical_id == logical_id) + } + + /// Find topology info by APIC ID + pub fn get_by_apic_id(&self, apic_id: u32) -> Option<&CpuTopologyInfo> { + self.cpus.iter().find(|cpu| cpu.apic_id == apic_id) + } + + /// Get total number of CPUs + pub fn cpu_count(&self) -> usize { + self.cpus.len() + } +} + +/// Detect extended CPU topology using CPUID leaves 1F or 0B +/// +/// This function properly handles modern Intel hybrid architectures by: +/// 1. Using CPUID leaf 1F (preferred) or 0B for extended topology +/// 2. Detecting hybrid architecture support (CPUID leaf 7) +/// 3. Identifying core types using CPUID leaf 1A +/// 4. Creating proper APIC ID to logical CPU ID mapping +pub fn detect_extended_topology() -> Result { + let cpuid = cpuid(); + + // Check if extended topology enumeration is available + let max_leaf = cpuid + .get_vendor_info() + .ok_or("CPUID vendor info not available")?; + + // Prefer CPUID leaf 1F over 0B for newer CPUs + let topology_leaf = if max_leaf.as_u32() >= 0x1F { + // Check if leaf 1F is valid (EBX != 0) + let leaf_1f = cpuid.get_extended_topology_info_v2(); + if leaf_1f.is_some() { + 0x1F + } else { + 0x0B + } + } else { + 0x0B + }; + + // Check for hybrid architecture support (CPUID leaf 7) + let is_hybrid = cpuid + .get_extended_feature_info() + .map(|features| features.has_hybrid()) + .unwrap_or(false); + + log::info!( + "CPU topology detection: leaf={:#x}, hybrid={}", + topology_leaf, + is_hybrid + ); + + // For now, create a simple mapping - this is a foundation that can be extended + // In a full implementation, we would enumerate all cores and build the complete topology + let current_apic_id = unsafe { crate::arch::device::local_apic::LOCAL_APIC.read().id() }; + + let current_core_type = if is_hybrid { + detect_current_core_type() + } else { + CoreType::Unknown + }; + + let topology_info = CpuTopologyInfo { + logical_id: 0, // BSP is always logical CPU 0 + apic_id: current_apic_id, + core_type: current_core_type, + smt_id: 0, // Simplified for now + core_id: 0, // Simplified for now + package_id: 0, // Simplified for now + }; + + Ok(TopologyMap { + cpus: alloc::vec![topology_info], + is_hybrid, + max_apic_id: current_apic_id, + }) +} + +/// Detect the core type of the current CPU using CPUID leaf 1A +fn detect_current_core_type() -> CoreType { + let cpuid = cpuid(); + + // CPUID leaf 1A provides hybrid information + // EAX[31:24] contains the core type + let hybrid_info = unsafe { + let result = core::arch::x86_64::__cpuid_count(0x1A, 0); + result.eax + }; + + let core_type_raw = (hybrid_info >> 24) & 0xFF; + + match core_type_raw { + 0x20 => CoreType::Efficiency, // E-core (Gracemont) + 0x40 => CoreType::Performance, // P-core (Golden Cove) + _ => CoreType::Unknown, + } +} + +/// Validate APIC ID consistency between ACPI MADT and CPUID +pub fn validate_apic_id_consistency(madt_apic_id: u32, cpuid_apic_id: u32) -> bool { + if madt_apic_id != cpuid_apic_id { + log::warn!( + "APIC ID mismatch: MADT reports {}, CPUID reports {}", + madt_apic_id, + cpuid_apic_id + ); + false + } else { + true + } +} diff --git a/src/asm/x86/trampoline.asm b/src/asm/x86/trampoline.asm index 6a11b404e..e20654fed 100644 --- a/src/asm/x86/trampoline.asm +++ b/src/asm/x86/trampoline.asm @@ -1,170 +1,170 @@ -; trampoline for bringing up APs -; compiled with nasm by build.rs, and included in src/acpi/madt.rs - -ORG 0x8000 -SECTION .text -USE16 - -trampoline: - jmp short startup_ap - times 8 - ($ - trampoline) nop - .ready: dq 0 - .cpu_id: dq 0 - .page_table: dq 0 - .stack_start: dq 0 - .stack_end: dq 0 - .code: dq 0 - -startup_ap: - cli - - xor ax, ax - mov ds, ax - mov es, ax - mov ss, ax - - ; initialize stack to invalid value - mov sp, 0 - - ; cr3 holds pointer to PML4 - mov edi, [trampoline.page_table] - mov cr3, edi - - ; enable FPU - mov eax, cr0 - and al, 11110011b ; Clear task switched (3) and emulation (2) - or al, 00100010b ; Set numeric error (5) monitor co-processor (1) - mov cr0, eax - - ; 9: FXSAVE/FXRSTOR - ; 7: Page Global - ; 4: Page Size Extension - mov eax, cr4 - or eax, 1 << 9 | 1 << 7 | 1 << 4 - mov cr4, eax - - ; initialize floating point registers - fninit - - ; load protected mode GDT - lgdt [gdtr] - - ;enabling paging and protection simultaneously - mov ebx, cr0 - ; 31: Paging - ; 16: write protect kernel - ; 0: Protected Mode - or ebx, 1 << 31 | 1 << 16 | 1 - mov cr0, ebx - - ; far jump to enable Protected Mode and load CS with 32 bit segment - jmp gdt.kernel_code:protected_mode_ap - -USE32 -protected_mode_ap: - mov eax, gdt.kernel_data - mov ds, eax - mov es, eax - mov fs, eax - mov gs, eax - mov ss, eax - - mov eax, [trampoline.stack_end] - lea esp, [eax - 256] - - mov eax, trampoline.cpu_id - push eax - - mov eax, [trampoline.code] - mov dword [trampoline.ready], 1 - call eax -.halt: - cli - hlt - jmp .halt - -struc GDTEntry - .limitl resw 1 - .basel resw 1 - .basem resb 1 - .attribute resb 1 - .flags__limith resb 1 - .baseh resb 1 -endstruc - -attrib: - .present equ 1 << 7 - .ring1 equ 1 << 5 - .ring2 equ 1 << 6 - .ring3 equ 1 << 5 | 1 << 6 - .user equ 1 << 4 -;user - .code equ 1 << 3 -; code - .conforming equ 1 << 2 - .readable equ 1 << 1 -; data - .expand_down equ 1 << 2 - .writable equ 1 << 1 - .accessed equ 1 << 0 -;system -; legacy - .tssAvailabe16 equ 0x1 - .ldt equ 0x2 - .tssBusy16 equ 0x3 - .call16 equ 0x4 - .task equ 0x5 - .interrupt16 equ 0x6 - .trap16 equ 0x7 - .tssAvailabe32 equ 0x9 - .tssBusy32 equ 0xB - .call32 equ 0xC - .interrupt32 equ 0xE - .trap32 equ 0xF -; long mode - .ldt32 equ 0x2 - .tssAvailabe64 equ 0x9 - .tssBusy64 equ 0xB - .call64 equ 0xC - .interrupt64 equ 0xE - .trap64 equ 0xF - -flags: - .granularity equ 1 << 7 - .available equ 1 << 4 -;user - .default_operand_size equ 1 << 6 -; code - .long_mode equ 1 << 5 -; data - .reserved equ 1 << 5 - -gdtr: - dw gdt.end + 1 ; size - dq gdt ; offset - -gdt: -.null equ $ - gdt - dq 0 - -.kernel_code equ $ - gdt -istruc GDTEntry - at GDTEntry.limitl, dw 0xFFFF - at GDTEntry.basel, dw 0 - at GDTEntry.basem, db 0 - at GDTEntry.attribute, db attrib.present | attrib.user | attrib.code | attrib.readable - at GDTEntry.flags__limith, db 0xF | flags.granularity | flags.default_operand_size - at GDTEntry.baseh, db 0 -iend - -.kernel_data equ $ - gdt -istruc GDTEntry - at GDTEntry.limitl, dw 0xFFFF - at GDTEntry.basel, dw 0 - at GDTEntry.basem, db 0 - at GDTEntry.attribute, db attrib.present | attrib.user | attrib.writable - at GDTEntry.flags__limith, db 0xF | flags.granularity | flags.default_operand_size - at GDTEntry.baseh, db 0 -iend - -.end equ $ - gdt +; trampoline for bringing up APs +; compiled with nasm by build.rs, and included in src/acpi/madt.rs + +ORG 0x8000 +SECTION .text +USE16 + +trampoline: + jmp short startup_ap + times 8 - ($ - trampoline) nop + .ready: dq 0 + .cpu_id: dq 0 + .page_table: dq 0 + .stack_start: dq 0 + .stack_end: dq 0 + .code: dq 0 + +startup_ap: + cli + + xor ax, ax + mov ds, ax + mov es, ax + mov ss, ax + + ; initialize stack to invalid value + mov sp, 0 + + ; cr3 holds pointer to PML4 + mov edi, [trampoline.page_table] + mov cr3, edi + + ; enable FPU + mov eax, cr0 + and al, 11110011b ; Clear task switched (3) and emulation (2) + or al, 00100010b ; Set numeric error (5) monitor co-processor (1) + mov cr0, eax + + ; 9: FXSAVE/FXRSTOR + ; 7: Page Global + ; 4: Page Size Extension + mov eax, cr4 + or eax, 1 << 9 | 1 << 7 | 1 << 4 + mov cr4, eax + + ; initialize floating point registers + fninit + + ; load protected mode GDT + lgdt [gdtr] + + ;enabling paging and protection simultaneously + mov ebx, cr0 + ; 31: Paging + ; 16: write protect kernel + ; 0: Protected Mode + or ebx, 1 << 31 | 1 << 16 | 1 + mov cr0, ebx + + ; far jump to enable Protected Mode and load CS with 32 bit segment + jmp gdt.kernel_code:protected_mode_ap + +USE32 +protected_mode_ap: + mov eax, gdt.kernel_data + mov ds, eax + mov es, eax + mov fs, eax + mov gs, eax + mov ss, eax + + mov eax, [trampoline.stack_end] + lea esp, [eax - 256] + + mov eax, trampoline.cpu_id + push eax + + mov eax, [trampoline.code] + mov dword [trampoline.ready], 1 + call eax +.halt: + cli + hlt + jmp .halt + +struc GDTEntry + .limitl resw 1 + .basel resw 1 + .basem resb 1 + .attribute resb 1 + .flags__limith resb 1 + .baseh resb 1 +endstruc + +attrib: + .present equ 1 << 7 + .ring1 equ 1 << 5 + .ring2 equ 1 << 6 + .ring3 equ 1 << 5 | 1 << 6 + .user equ 1 << 4 +;user + .code equ 1 << 3 +; code + .conforming equ 1 << 2 + .readable equ 1 << 1 +; data + .expand_down equ 1 << 2 + .writable equ 1 << 1 + .accessed equ 1 << 0 +;system +; legacy + .tssAvailabe16 equ 0x1 + .ldt equ 0x2 + .tssBusy16 equ 0x3 + .call16 equ 0x4 + .task equ 0x5 + .interrupt16 equ 0x6 + .trap16 equ 0x7 + .tssAvailabe32 equ 0x9 + .tssBusy32 equ 0xB + .call32 equ 0xC + .interrupt32 equ 0xE + .trap32 equ 0xF +; long mode + .ldt32 equ 0x2 + .tssAvailabe64 equ 0x9 + .tssBusy64 equ 0xB + .call64 equ 0xC + .interrupt64 equ 0xE + .trap64 equ 0xF + +flags: + .granularity equ 1 << 7 + .available equ 1 << 4 +;user + .default_operand_size equ 1 << 6 +; code + .long_mode equ 1 << 5 +; data + .reserved equ 1 << 5 + +gdtr: + dw gdt.end + 1 ; size + dq gdt ; offset + +gdt: +.null equ $ - gdt + dq 0 + +.kernel_code equ $ - gdt +istruc GDTEntry + at GDTEntry.limitl, dw 0xFFFF + at GDTEntry.basel, dw 0 + at GDTEntry.basem, db 0 + at GDTEntry.attribute, db attrib.present | attrib.user | attrib.code | attrib.readable + at GDTEntry.flags__limith, db 0xF | flags.granularity | flags.default_operand_size + at GDTEntry.baseh, db 0 +iend + +.kernel_data equ $ - gdt +istruc GDTEntry + at GDTEntry.limitl, dw 0xFFFF + at GDTEntry.basel, dw 0 + at GDTEntry.basem, db 0 + at GDTEntry.attribute, db attrib.present | attrib.user | attrib.writable + at GDTEntry.flags__limith, db 0xF | flags.granularity | flags.default_operand_size + at GDTEntry.baseh, db 0 +iend + +.end equ $ - gdt diff --git a/src/asm/x86_64/trampoline.asm b/src/asm/x86_64/trampoline.asm index 538ff1b79..e073f379d 100644 --- a/src/asm/x86_64/trampoline.asm +++ b/src/asm/x86_64/trampoline.asm @@ -1,173 +1,173 @@ -; trampoline for bringing up APs -; compiled with nasm by build.rs, and included in src/acpi/madt.rs - -ORG 0x8000 -SECTION .text -USE16 - -trampoline: - jmp short startup_ap - times 8 - ($ - trampoline) nop - .ready: dq 0 - .cpu_id: dq 0 - .page_table: dq 0 - .stack_start: dq 0 - .stack_end: dq 0 - .code: dq 0 - -startup_ap: - cli - - xor ax, ax - mov ds, ax - mov es, ax - mov ss, ax - - ; initialize stack to invalid value - mov sp, 0 - - ; cr3 holds pointer to PML4 - mov edi, [trampoline.page_table] - mov cr3, edi - - ; enable FPU - mov eax, cr0 - and al, 11110011b ; Clear task switched (3) and emulation (2) - or al, 00100010b ; Set numeric error (5) monitor co-processor (1) - mov cr0, eax - - ; 9: FXSAVE/FXRSTOR - ; 7: Page Global - ; 5: Page Address Extension - ; 4: Page Size Extension - mov eax, cr4 - or eax, 1 << 9 | 1 << 7 | 1 << 5 | 1 << 4 - mov cr4, eax - - ; initialize floating point registers - fninit - - ; load protected mode GDT - lgdt [gdtr] - - ; enable long mode - mov ecx, 0xC0000080 ; Read from the EFER MSR. - rdmsr - or eax, 1 << 11 | 1 << 8 ; Set the Long-Mode-Enable and NXE bit. - wrmsr - - ; enabling paging and protection simultaneously - mov ebx, cr0 - ; 31: Paging - ; 16: write protect kernel - ; 0: Protected Mode - or ebx, 1 << 31 | 1 << 16 | 1 - mov cr0, ebx - - ; far jump to enable Long Mode and load CS with 64 bit segment - jmp gdt.kernel_code:long_mode_ap - -USE64 -long_mode_ap: - mov rax, gdt.kernel_data - mov ds, rax - mov es, rax - mov fs, rax - mov gs, rax - mov ss, rax - - mov rcx, [trampoline.stack_end] - lea rsp, [rcx - 256] - - mov rdi, trampoline.cpu_id - - mov rax, [trampoline.code] - mov qword [trampoline.ready], 1 - jmp rax - -struc GDTEntry - .limitl resw 1 - .basel resw 1 - .basem resb 1 - .attribute resb 1 - .flags__limith resb 1 - .baseh resb 1 -endstruc - -attrib: - .present equ 1 << 7 - .ring1 equ 1 << 5 - .ring2 equ 1 << 6 - .ring3 equ 1 << 5 | 1 << 6 - .user equ 1 << 4 -;user - .code equ 1 << 3 -; code - .conforming equ 1 << 2 - .readable equ 1 << 1 -; data - .expand_down equ 1 << 2 - .writable equ 1 << 1 - .accessed equ 1 << 0 -;system -; legacy - .tssAvailabe16 equ 0x1 - .ldt equ 0x2 - .tssBusy16 equ 0x3 - .call16 equ 0x4 - .task equ 0x5 - .interrupt16 equ 0x6 - .trap16 equ 0x7 - .tssAvailabe32 equ 0x9 - .tssBusy32 equ 0xB - .call32 equ 0xC - .interrupt32 equ 0xE - .trap32 equ 0xF -; long mode - .ldt32 equ 0x2 - .tssAvailabe64 equ 0x9 - .tssBusy64 equ 0xB - .call64 equ 0xC - .interrupt64 equ 0xE - .trap64 equ 0xF - -flags: - .granularity equ 1 << 7 - .available equ 1 << 4 -;user - .default_operand_size equ 1 << 6 -; code - .long_mode equ 1 << 5 -; data - .reserved equ 1 << 5 - -gdtr: - dw gdt.end + 1 ; size - dq gdt ; offset - -gdt: -.null equ $ - gdt - dq 0 - -.kernel_code equ $ - gdt -istruc GDTEntry - at GDTEntry.limitl, dw 0 - at GDTEntry.basel, dw 0 - at GDTEntry.basem, db 0 - at GDTEntry.attribute, db attrib.present | attrib.user | attrib.code - at GDTEntry.flags__limith, db flags.long_mode - at GDTEntry.baseh, db 0 -iend - -.kernel_data equ $ - gdt -istruc GDTEntry - at GDTEntry.limitl, dw 0 - at GDTEntry.basel, dw 0 - at GDTEntry.basem, db 0 -; AMD System Programming Manual states that the writeable bit is ignored in long mode, but ss can not be set to this descriptor without it - at GDTEntry.attribute, db attrib.present | attrib.user | attrib.writable - at GDTEntry.flags__limith, db 0 - at GDTEntry.baseh, db 0 -iend - -.end equ $ - gdt +; trampoline for bringing up APs +; compiled with nasm by build.rs, and included in src/acpi/madt.rs + +ORG 0x8000 +SECTION .text +USE16 + +trampoline: + jmp short startup_ap + times 8 - ($ - trampoline) nop + .ready: dq 0 + .cpu_id: dq 0 + .page_table: dq 0 + .stack_start: dq 0 + .stack_end: dq 0 + .code: dq 0 + +startup_ap: + cli + + xor ax, ax + mov ds, ax + mov es, ax + mov ss, ax + + ; initialize stack to invalid value + mov sp, 0 + + ; cr3 holds pointer to PML4 + mov edi, [trampoline.page_table] + mov cr3, edi + + ; enable FPU + mov eax, cr0 + and al, 11110011b ; Clear task switched (3) and emulation (2) + or al, 00100010b ; Set numeric error (5) monitor co-processor (1) + mov cr0, eax + + ; 9: FXSAVE/FXRSTOR + ; 7: Page Global + ; 5: Page Address Extension + ; 4: Page Size Extension + mov eax, cr4 + or eax, 1 << 9 | 1 << 7 | 1 << 5 | 1 << 4 + mov cr4, eax + + ; initialize floating point registers + fninit + + ; load protected mode GDT + lgdt [gdtr] + + ; enable long mode + mov ecx, 0xC0000080 ; Read from the EFER MSR. + rdmsr + or eax, 1 << 11 | 1 << 8 ; Set the Long-Mode-Enable and NXE bit. + wrmsr + + ; enabling paging and protection simultaneously + mov ebx, cr0 + ; 31: Paging + ; 16: write protect kernel + ; 0: Protected Mode + or ebx, 1 << 31 | 1 << 16 | 1 + mov cr0, ebx + + ; far jump to enable Long Mode and load CS with 64 bit segment + jmp gdt.kernel_code:long_mode_ap + +USE64 +long_mode_ap: + mov rax, gdt.kernel_data + mov ds, rax + mov es, rax + mov fs, rax + mov gs, rax + mov ss, rax + + mov rcx, [trampoline.stack_end] + lea rsp, [rcx - 256] + + mov rdi, trampoline.cpu_id + + mov rax, [trampoline.code] + mov qword [trampoline.ready], 1 + jmp rax + +struc GDTEntry + .limitl resw 1 + .basel resw 1 + .basem resb 1 + .attribute resb 1 + .flags__limith resb 1 + .baseh resb 1 +endstruc + +attrib: + .present equ 1 << 7 + .ring1 equ 1 << 5 + .ring2 equ 1 << 6 + .ring3 equ 1 << 5 | 1 << 6 + .user equ 1 << 4 +;user + .code equ 1 << 3 +; code + .conforming equ 1 << 2 + .readable equ 1 << 1 +; data + .expand_down equ 1 << 2 + .writable equ 1 << 1 + .accessed equ 1 << 0 +;system +; legacy + .tssAvailabe16 equ 0x1 + .ldt equ 0x2 + .tssBusy16 equ 0x3 + .call16 equ 0x4 + .task equ 0x5 + .interrupt16 equ 0x6 + .trap16 equ 0x7 + .tssAvailabe32 equ 0x9 + .tssBusy32 equ 0xB + .call32 equ 0xC + .interrupt32 equ 0xE + .trap32 equ 0xF +; long mode + .ldt32 equ 0x2 + .tssAvailabe64 equ 0x9 + .tssBusy64 equ 0xB + .call64 equ 0xC + .interrupt64 equ 0xE + .trap64 equ 0xF + +flags: + .granularity equ 1 << 7 + .available equ 1 << 4 +;user + .default_operand_size equ 1 << 6 +; code + .long_mode equ 1 << 5 +; data + .reserved equ 1 << 5 + +gdtr: + dw gdt.end + 1 ; size + dq gdt ; offset + +gdt: +.null equ $ - gdt + dq 0 + +.kernel_code equ $ - gdt +istruc GDTEntry + at GDTEntry.limitl, dw 0 + at GDTEntry.basel, dw 0 + at GDTEntry.basem, db 0 + at GDTEntry.attribute, db attrib.present | attrib.user | attrib.code + at GDTEntry.flags__limith, db flags.long_mode + at GDTEntry.baseh, db 0 +iend + +.kernel_data equ $ - gdt +istruc GDTEntry + at GDTEntry.limitl, dw 0 + at GDTEntry.basel, dw 0 + at GDTEntry.basem, db 0 +; AMD System Programming Manual states that the writeable bit is ignored in long mode, but ss can not be set to this descriptor without it + at GDTEntry.attribute, db attrib.present | attrib.user | attrib.writable + at GDTEntry.flags__limith, db 0 + at GDTEntry.baseh, db 0 +iend + +.end equ $ - gdt diff --git a/src/context/memory.rs b/src/context/memory.rs index 6234d6739..5b211e22c 100644 --- a/src/context/memory.rs +++ b/src/context/memory.rs @@ -1228,7 +1228,7 @@ impl Grant { unsafe { let result = mapper .map_phys(page.start_address(), frame.base(), flags) - .expect("TODO: page table OOM"); + .expect("page table allocation must succeed for valid memory operation"); result.ignore(); flusher.queue(frame, None, TlbShootdownActions::NEW_MAPPING); diff --git a/src/cpu_set.rs b/src/cpu_set.rs index 80060f94a..fe655e3be 100644 --- a/src/cpu_set.rs +++ b/src/cpu_set.rs @@ -106,14 +106,14 @@ impl ToString for LogicalCpuSet { let words = raw.get(..(cpu_count / usize::BITS) as usize).unwrap_or(&[]); for (i, word) in words.iter().enumerate() { if i != 0 { - write!(ret, "_").unwrap(); + write!(ret, "_").expect("writing to String never fails"); } let word = if i == words.len() - 1 { *word & ((1_usize << (cpu_count % usize::BITS)) - 1) } else { *word }; - write!(ret, "{word:x}").unwrap(); + write!(ret, "{word:x}").expect("writing to String never fails"); } ret } diff --git a/src/cpu_topology.rs b/src/cpu_topology.rs new file mode 100644 index 000000000..cecaa4051 --- /dev/null +++ b/src/cpu_topology.rs @@ -0,0 +1,162 @@ +/// Global CPU topology management for multi-core support +/// +/// This module provides a centralized way to manage CPU topology information, +/// especially for modern hybrid architectures like Intel Alder Lake. +use crate::cpu_set::LogicalCpuId; +use alloc::vec::Vec; +use spin::Mutex; + +#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] +use crate::arch::x86_shared::topology::{CoreType, CpuTopologyInfo, TopologyMap}; + +/// Global CPU topology information +static CPU_TOPOLOGY: Mutex> = Mutex::new(None); + +/// CPU topology data for the entire system +#[derive(Debug)] +pub struct CpuTopologyData { + /// Per-CPU topology information + pub cpus: Vec, + /// Whether this system has hybrid architecture + pub is_hybrid: bool, + /// Total number of CPUs detected + pub total_cpus: usize, + /// Number of Performance cores + pub p_core_count: usize, + /// Number of Efficiency cores + pub e_core_count: usize, +} + +impl CpuTopologyData { + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + fn from_topology_map(map: TopologyMap) -> Self { + let p_core_count = map + .cpus + .iter() + .filter(|cpu| cpu.core_type == CoreType::Performance) + .count(); + let e_core_count = map + .cpus + .iter() + .filter(|cpu| cpu.core_type == CoreType::Efficiency) + .count(); + + Self { + total_cpus: map.cpu_count(), + is_hybrid: map.is_hybrid, + p_core_count, + e_core_count, + cpus: map.cpus, + } + } +} + +/// Initialize CPU topology detection +/// +/// This should be called early in kernel initialization to detect +/// the CPU topology and set up proper APIC ID mapping. +pub fn init_cpu_topology() -> Result<(), &'static str> { + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + { + let topology_map = crate::arch::x86_shared::topology::detect_extended_topology()?; + + log::info!("CPU Topology detected:"); + log::info!(" Total CPUs: {}", topology_map.cpu_count()); + log::info!(" Hybrid architecture: {}", topology_map.is_hybrid); + log::info!(" Max APIC ID: {}", topology_map.max_apic_id); + + if topology_map.is_hybrid { + let p_cores = topology_map + .cpus + .iter() + .filter(|cpu| cpu.core_type == CoreType::Performance) + .count(); + let e_cores = topology_map + .cpus + .iter() + .filter(|cpu| cpu.core_type == CoreType::Efficiency) + .count(); + log::info!(" P-cores: {}, E-cores: {}", p_cores, e_cores); + } + + let topology_data = CpuTopologyData::from_topology_map(topology_map); + *CPU_TOPOLOGY.lock() = Some(topology_data); + + Ok(()) + } + + #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))] + { + log::info!("CPU topology detection not implemented for this architecture"); + Ok(()) + } +} + +/// Get APIC ID for a given logical CPU ID +/// +/// This is critical for multi-core initialization where we need to send +/// IPIs to specific cores using their APIC IDs. +pub fn get_apic_id_for_logical_cpu(logical_id: LogicalCpuId) -> Option { + let topology = CPU_TOPOLOGY.lock(); + if let Some(ref data) = *topology { + data.cpus + .iter() + .find(|cpu| cpu.logical_id == logical_id.get()) + .map(|cpu| cpu.apic_id) + } else { + None + } +} + +/// Get logical CPU ID for a given APIC ID +/// +/// This is used when an AP (Application Processor) starts up and needs +/// to determine its logical CPU ID from its APIC ID. +pub fn get_logical_cpu_for_apic_id(apic_id: u32) -> Option { + let topology = CPU_TOPOLOGY.lock(); + if let Some(ref data) = *topology { + data.cpus + .iter() + .find(|cpu| cpu.apic_id == apic_id) + .map(|cpu| LogicalCpuId::new(cpu.logical_id)) + } else { + None + } +} + +/// Check if the current system has hybrid architecture +pub fn is_hybrid_architecture() -> bool { + let topology = CPU_TOPOLOGY.lock(); + topology + .as_ref() + .map(|data| data.is_hybrid) + .unwrap_or(false) +} + +/// Get the core type for a given logical CPU ID +#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] +pub fn get_core_type(logical_id: LogicalCpuId) -> Option { + let topology = CPU_TOPOLOGY.lock(); + if let Some(ref data) = *topology { + data.cpus + .iter() + .find(|cpu| cpu.logical_id == logical_id.get()) + .map(|cpu| cpu.core_type) + } else { + None + } +} + +/// Validate that an APIC ID from ACPI matches our detected topology +/// +/// This helps catch firmware bugs or inconsistencies between ACPI +/// and CPUID-reported topology information. +pub fn validate_acpi_apic_id(acpi_apic_id: u32) -> bool { + let topology = CPU_TOPOLOGY.lock(); + if let Some(ref data) = *topology { + data.cpus.iter().any(|cpu| cpu.apic_id == acpi_apic_id) + } else { + // If topology not initialized, assume valid (fallback behavior) + true + } +} diff --git a/src/main.rs b/src/main.rs index a5ba4be38..fe39fdfd0 100644 --- a/src/main.rs +++ b/src/main.rs @@ -34,8 +34,8 @@ // TODO: address ocurrances and then deny #![warn(clippy::integer_arithmetic)] // Avoid panicking in the kernel without information about the panic. Use expect -// TODO: address ocurrances and then deny -#![warn(clippy::result_unwrap_used)] +// Enabled: This critical security lint prevents unexpected panics in kernel space +#![deny(clippy::result_unwrap_used)] // This is usually a serious issue - a missing import of a define where it is interpreted // as a catch-all variable in a match, for example #![deny(unreachable_patterns)] @@ -93,6 +93,9 @@ mod cpu_set; #[cfg(feature = "sys_stat")] mod cpu_stats; +/// CPU topology management for multi-core support +mod cpu_topology; + /// Context management mod context; @@ -191,6 +194,12 @@ fn kmain(cpu_count: u32, bootstrap: Bootstrap) -> ! { //Initialize the first context, stored in kernel/src/context/mod.rs context::init(); + // Initialize CPU topology detection for multi-core support + if let Err(e) = cpu_topology::init_cpu_topology() { + log::warn!("CPU topology detection failed: {}", e); + log::warn!("Multi-core support may be limited on hybrid CPUs"); + } + //Initialize global schemes, such as `acpi:`. scheme::init_globals(); @@ -232,10 +241,48 @@ fn kmain_ap(cpu_id: crate::cpu_set::LogicalCpuId) -> ! { #[cfg(feature = "profiling")] profiling::maybe_run_profiling_helper_forever(cpu_id); - //TODO: workaround for bug where an AP on MeteorLake has cpu_id 0 - if !cfg!(feature = "multi_core") || cpu_id == crate::cpu_set::LogicalCpuId::BSP { - info!("AP {}: Disabled", cpu_id); + // Enhanced multi-core support with topology-aware APIC ID handling + if !cfg!(feature = "multi_core") { + info!("AP {}: Multi-core disabled, halting AP", cpu_id); + } else if cpu_id == crate::cpu_set::LogicalCpuId::BSP { + // Get current APIC ID for detailed diagnosis + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + let current_apic_id = unsafe { crate::arch::device::local_apic::LOCAL_APIC.read().id() }; + #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))] + let current_apic_id = 0; + + warn!( + "AP {}: Unexpected BSP CPU ID on AP - APIC ID mismatch detected", + cpu_id + ); + warn!(" Current APIC ID: {}", current_apic_id); + + // Try to find correct logical CPU ID from topology + if let Some(correct_logical_id) = + crate::cpu_topology::get_logical_cpu_for_apic_id(current_apic_id) + { + warn!( + " Topology suggests logical CPU ID should be: {}", + correct_logical_id + ); + info!( + " Hybrid architecture: {}", + crate::cpu_topology::is_hybrid_architecture() + ); + + #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] + if let Some(core_type) = crate::cpu_topology::get_core_type(correct_logical_id) { + info!(" Core type: {}", core_type); + } + } else { + warn!( + " APIC ID {} not found in detected topology - possible firmware issue", + current_apic_id + ); + } + } + if !cfg!(feature = "multi_core") || cpu_id == crate::cpu_set::LogicalCpuId::BSP { loop { unsafe { interrupt::disable(); diff --git a/src/memory/mod.rs b/src/memory/mod.rs index bf294ed4a..81d022681 100644 --- a/src/memory/mod.rs +++ b/src/memory/mod.rs @@ -57,10 +57,25 @@ pub fn total_frames() -> usize { sections().iter().map(|section| section.frames.len()).sum() } -/// Allocate a range of frames +/// Allocate a range of frames with specified power-of-2 order +/// +/// # Arguments +/// * `order` - Power of 2 order determining the number of contiguous frames (2^order) +/// +/// # Returns +/// * `Some(Frame)` - First frame of the allocated range +/// * `None` - If allocation fails due to insufficient memory pub fn allocate_p2frame(order: u32) -> Option { allocate_p2frame_complex(order, (), None, order).map(|(f, _)| f) } + +/// Allocate a single frame +/// +/// This is a convenience function equivalent to `allocate_p2frame(0)`. +/// +/// # Returns +/// * `Some(Frame)` - The allocated frame +/// * `None` - If no frames are available pub fn allocate_frame() -> Option { allocate_p2frame(0) } @@ -318,9 +333,7 @@ impl Frame { pub fn range_inclusive(start: Frame, end: Frame) -> impl Iterator { (start.physaddr.get()..=end.physaddr.get()) .step_by(PAGE_SIZE) - .map(|number| Frame { - physaddr: NonZeroUsize::new(number).unwrap(), - }) + .filter_map(|number| NonZeroUsize::new(number).map(|physaddr| Frame { physaddr })) } #[track_caller] pub fn next_by(self, n: usize) -> Self { @@ -977,6 +990,23 @@ pub trait ArchIntCtx { fn recover_and_efault(&mut self); } +/// Handle page faults by attempting to resolve them through memory grants +/// +/// This is a critical security function that validates memory accesses and +/// provides demand paging for mapped but unallocated memory regions. +/// +/// # Arguments +/// * `stack` - Architecture-specific interrupt context for potential error recovery +/// * `code` - Page fault flags indicating the type of fault (read/write, user/kernel, etc.) +/// * `faulting_address` - Virtual address that caused the page fault +/// +/// # Returns +/// * `Ok(())` - Page fault was successfully resolved +/// * `Err(Segv)` - Invalid memory access that should trigger a segmentation fault +/// +/// # Security Notes +/// This function performs critical security checks to prevent unauthorized memory access. +/// It validates permissions and ensures proper isolation between processes. pub fn page_fault_handler( stack: &mut impl ArchIntCtx, code: GenericPfFlags, diff --git a/targets/aarch64-unknown-kernel.json b/targets/aarch64-unknown-kernel.json index 74e4b9f01..568f30f6d 100644 --- a/targets/aarch64-unknown-kernel.json +++ b/targets/aarch64-unknown-kernel.json @@ -1,24 +1,24 @@ -{ - "llvm-target": "aarch64-unknown-none", - "abi": "softfloat", - "target-endian": "little", - "target-pointer-width": "64", - "target-c-int-width": "32", - "data-layout": "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32", - "arch": "aarch64", - "os": "none", - "env": "", - "vendor": "unknown", - "linker": "rust-lld", - "linker-flavor": "gnu-lld", - "features": "+strict-align,-neon,-fp-armv8,+tpidr-el1", - "dynamic-linking": false, - "executables": true, - "relocation-model": "pic", - "disable-redzone": true, - "frame-pointer": "always", - "exe-suffix": "", - "has-rpath": false, - "no-default-libraries": true, - "position-independent-executables": false -} +{ + "llvm-target": "aarch64-unknown-none", + "abi": "softfloat", + "target-endian": "little", + "target-pointer-width": "64", + "target-c-int-width": "32", + "data-layout": "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32", + "arch": "aarch64", + "os": "none", + "env": "", + "vendor": "unknown", + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "features": "+strict-align,-neon,-fp-armv8,+tpidr-el1", + "dynamic-linking": false, + "executables": true, + "relocation-model": "pic", + "disable-redzone": true, + "frame-pointer": "always", + "exe-suffix": "", + "has-rpath": false, + "no-default-libraries": true, + "position-independent-executables": false +} diff --git a/targets/i686-unknown-kernel.json b/targets/i686-unknown-kernel.json index 141844add..2156be0f9 100644 --- a/targets/i686-unknown-kernel.json +++ b/targets/i686-unknown-kernel.json @@ -1,24 +1,24 @@ -{ - "llvm-target": "i686-unknown-none", - "target-endian": "little", - "target-pointer-width": "32", - "target-c-int-width": "32", - "data-layout": "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:32-n8:16:32-S128", - "arch": "x86", - "os": "none", - "env": "", - "vendor": "unknown", - "linker": "rust-lld", - "linker-flavor": "gnu-lld", - "features": "-mmx,-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2,+soft-float", - "dynamic-linking": false, - "executables": true, - "relocation-model": "static", - "code-model": "kernel", - "disable-redzone": true, - "frame-pointer": "always", - "exe-suffix": "", - "has-rpath": false, - "no-default-libraries": true, - "position-independent-executables": false -} +{ + "llvm-target": "i686-unknown-none", + "target-endian": "little", + "target-pointer-width": "32", + "target-c-int-width": "32", + "data-layout": "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:32-n8:16:32-S128", + "arch": "x86", + "os": "none", + "env": "", + "vendor": "unknown", + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "features": "-mmx,-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2,+soft-float", + "dynamic-linking": false, + "executables": true, + "relocation-model": "static", + "code-model": "kernel", + "disable-redzone": true, + "frame-pointer": "always", + "exe-suffix": "", + "has-rpath": false, + "no-default-libraries": true, + "position-independent-executables": false +} diff --git a/targets/riscv64-unknown-kernel.json b/targets/riscv64-unknown-kernel.json index c9ac6f625..af11fe6c9 100644 --- a/targets/riscv64-unknown-kernel.json +++ b/targets/riscv64-unknown-kernel.json @@ -1,24 +1,24 @@ -{ - "llvm-target": "riscv64-unknown-none", - "llvm-abiname": "lp64", - "target-endian": "little", - "target-pointer-width": "64", - "target-c-int-width": "32", - "data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128", - "arch": "riscv64", - "os": "none", - "env": "", - "vendor": "unknown", - "linker": "rust-lld", - "linker-flavor": "gnu-lld", - "features": "+m,+a,+c,+zihintpause", - "dynamic-linking": false, - "executables": true, - "relocation-model": "pic", - "disable-redzone": true, - "frame-pointer": "always", - "exe-suffix": "", - "has-rpath": false, - "no-default-libraries": true, - "position-independent-executables": false -} +{ + "llvm-target": "riscv64-unknown-none", + "llvm-abiname": "lp64", + "target-endian": "little", + "target-pointer-width": "64", + "target-c-int-width": "32", + "data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128", + "arch": "riscv64", + "os": "none", + "env": "", + "vendor": "unknown", + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "features": "+m,+a,+c,+zihintpause", + "dynamic-linking": false, + "executables": true, + "relocation-model": "pic", + "disable-redzone": true, + "frame-pointer": "always", + "exe-suffix": "", + "has-rpath": false, + "no-default-libraries": true, + "position-independent-executables": false +} diff --git a/targets/x86_64-unknown-kernel.json b/targets/x86_64-unknown-kernel.json index 848ef0e19..e57026642 100644 --- a/targets/x86_64-unknown-kernel.json +++ b/targets/x86_64-unknown-kernel.json @@ -1,24 +1,24 @@ -{ - "llvm-target": "x86_64-unknown-none", - "target-endian": "little", - "target-pointer-width": "64", - "target-c-int-width": "32", - "data-layout": "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", - "arch": "x86_64", - "os": "none", - "env": "", - "vendor": "unknown", - "linker": "rust-lld", - "linker-flavor": "gnu-lld", - "features": "-mmx,-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2,+soft-float", - "dynamic-linking": false, - "executables": true, - "relocation-model": "static", - "code-model": "kernel", - "disable-redzone": true, - "frame-pointer": "always", - "exe-suffix": "", - "has-rpath": false, - "no-default-libraries": true, - "position-independent-executables": false -} +{ + "llvm-target": "x86_64-unknown-none", + "target-endian": "little", + "target-pointer-width": "64", + "target-c-int-width": "32", + "data-layout": "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", + "arch": "x86_64", + "os": "none", + "env": "", + "vendor": "unknown", + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "features": "-mmx,-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2,+soft-float", + "dynamic-linking": false, + "executables": true, + "relocation-model": "static", + "code-model": "kernel", + "disable-redzone": true, + "frame-pointer": "always", + "exe-suffix": "", + "has-rpath": false, + "no-default-libraries": true, + "position-independent-executables": false +}