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driver: gpio: Add initial gpio drirver support for RA8M1
This is the initial commit to support for gpio driver for RA8M1 MCU, the coding is base on renesas fsp hal Signed-off-by: Duy Nguyen <[email protected]>
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‎drivers/gpio/CMakeLists.txt‎

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@@ -90,6 +90,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711 gpio_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ENE_KB1200 gpio_ene_kb1200.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RA8 gpio_renesas_ra8.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RZT2M gpio_rzt2m.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ gpio_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BRCMSTB gpio_brcmstb.c)

‎drivers/gpio/Kconfig‎

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@@ -238,6 +238,8 @@ source "drivers/gpio/Kconfig.renesas_ra"
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source "drivers/gpio/Kconfig.ene"
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source "drivers/gpio/Kconfig.renesas_ra8"
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source "drivers/gpio/Kconfig.rzt2m"
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source "drivers/gpio/Kconfig.ambiq"

‎drivers/gpio/Kconfig.renesas_ra8‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_RA8
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bool "Renesas RA8 GPIO driver"
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default y
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depends on DT_HAS_RENESAS_RA8_GPIO_ENABLED
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help
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Enable the Renesas RA8 GPIO driver.

‎drivers/gpio/gpio_renesas_ra8.c‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra8_gpio
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#define PRCR_KEY 0xA500U
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#define VBATT_PORT 4
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static const gpio_pin_t vbatt_pins[] = {
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2U,
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3U,
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4U,
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};
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#define RA8_INVALID_PORT_ADDR 0UL
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#define RA8_GPIO_PORT_ADDR(nodelabel) \
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COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
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(DT_REG_ADDR(DT_NODELABEL(nodelabel))), (RA8_INVALID_PORT_ADDR))
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struct gpio_ra8_config {
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struct gpio_driver_config common;
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uint8_t port_num;
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R_PORT0_Type *port;
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};
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struct gpio_ra8_data {
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struct gpio_driver_data common;
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};
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static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_ra8_config *config = dev->config;
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if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_PULL_DOWN) != 0U) {
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return -ENOTSUP;
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}
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if (config->port_num == VBATT_PORT) {
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uint32_t clear = 0;
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for (int i = 0; i < ARRAY_SIZE(vbatt_pins); i++) {
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if (vbatt_pins[i] == pin) {
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WRITE_BIT(clear, i, 1);
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}
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}
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R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | PRCR_KEY) | R_SYSTEM_PRCR_PRC1_Msk);
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R_SYSTEM->VBTICTLR &= (uint8_t)~clear;
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R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | PRCR_KEY) & (uint16_t)~R_SYSTEM_PRCR_PRC1_Msk);
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}
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#if BSP_CFG_MCU_PART_SERIES == 8
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R_PMISC->PWPRS = 0;
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R_PMISC->PWPRS = BIT(R_PMISC_PWPR_PFSWE_Pos);
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#else
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R_PMISC->PWPR = 0;
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R_PMISC->PWPR = BIT(R_PMISC_PWPR_PFSWE_Pos);
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#endif
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uint32_t value = R_PFS->PORT[config->port_num].PIN[pin].PmnPFS;
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/* Change mode to general IO mode and disable IRQ and Analog input */
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_PMR_Pos, 0);
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_ASEL_Pos, 0);
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 0);
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if ((flags & GPIO_OUTPUT) != 0U) {
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/* Set output pin initial value */
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if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 0);
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} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 1);
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}
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 1);
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} else {
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WRITE_BIT(value, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 0);
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}
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R_PFS->PORT[config->port_num].PIN[pin].PmnPFS = value;
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#if BSP_CFG_MCU_PART_SERIES == 8
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R_PMISC->PWPRS = 0;
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R_PMISC->PWPRS = BIT(R_PMISC_PWPR_B0WI_Pos);
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#else
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R_PMISC->PWPR = 0;
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R_PMISC->PWPR = BIT(R_PMISC_PWPR_B0WI_Pos);
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#endif
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return 0;
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}
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static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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*value = port->PIDR;
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return 0;
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}
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static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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port->PODR = ((port->PODR & ~mask) | (value & mask));
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return 0;
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}
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static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
131+
{
132+
const struct gpio_ra8_config *config = dev->config;
133+
R_PORT0_Type *port = config->port;
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port->PODR = (port->PODR | pins);
136+
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return 0;
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}
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static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
141+
{
142+
const struct gpio_ra8_config *config = dev->config;
143+
R_PORT0_Type *port = config->port;
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port->PODR = (port->PODR & ~pins);
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return 0;
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}
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static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
151+
{
152+
const struct gpio_ra8_config *config = dev->config;
153+
R_PORT0_Type *port = config->port;
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port->PODR = (port->PODR ^ pins);
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return 0;
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}
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static const struct gpio_driver_api gpio_ra8_drv_api_funcs = {
161+
.pin_configure = gpio_ra8_pin_configure,
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.port_get_raw = gpio_ra8_port_get_raw,
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.port_set_masked_raw = gpio_ra8_port_set_masked_raw,
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.port_set_bits_raw = gpio_ra8_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ra8_port_clear_bits_raw,
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.port_toggle_bits = gpio_ra8_port_toggle_bits,
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.pin_interrupt_configure = NULL,
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.manage_callback = NULL,
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#ifdef CONFIG_GPIO_GET_DIRECTION
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.port_get_direction = gpio_ra8_port_get_direction,
171+
#endif
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};
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static int gpio_ra8_init(const struct device *dev)
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{
176+
return 0;
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}
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#define GPIO_DEVICE_INIT(__node, __port_num, __suffix, __addr) \
180+
static const struct gpio_ra8_config gpio_ra8_config_##__suffix = { \
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.common = \
182+
{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
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}, \
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.port_num = __port_num, \
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.port = (R_PORT0_Type *)__addr, \
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}; \
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static struct gpio_ra8_data gpio_ra8_data_##__suffix; \
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DEVICE_DT_DEFINE(__node, gpio_ra8_init, PM_DEVICE_DT_GET(__node), \
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&gpio_ra8_data_##__suffix, &gpio_ra8_config_##__suffix, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, &gpio_ra8_drv_api_funcs)
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#define GPIO_DEVICE_INIT_RA8(__suffix) \
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GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), \
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DT_PROP(DT_NODELABEL(gpio##__suffix), port), __suffix, \
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DT_REG_ADDR(DT_NODELABEL(gpio##__suffix)))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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GPIO_DEVICE_INIT_RA8(0);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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GPIO_DEVICE_INIT_RA8(1);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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GPIO_DEVICE_INIT_RA8(2);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
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GPIO_DEVICE_INIT_RA8(3);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
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GPIO_DEVICE_INIT_RA8(4);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
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GPIO_DEVICE_INIT_RA8(5);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
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GPIO_DEVICE_INIT_RA8(6);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
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GPIO_DEVICE_INIT_RA8(7);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay)
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GPIO_DEVICE_INIT_RA8(8);
232+
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay)
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GPIO_DEVICE_INIT_RA8(9);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
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GPIO_DEVICE_INIT_RA8(a);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
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GPIO_DEVICE_INIT_RA8(b);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */

‎dts/arm/renesas/ra/ra8/ra8x1.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -47,6 +47,126 @@
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reg = <0x40400800 0x3c0>;
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status = "disabled";
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};
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gpio0: gpio@40400000 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpio1: gpio@40400020 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400020 0x20>;
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port = <1>;
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gpio-controller;
66+
#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpio2: gpio@40400040 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400040 0x20>;
74+
port = <2>;
75+
gpio-controller;
76+
#gpio-cells = <2>;
77+
ngpios = <16>;
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status = "disabled";
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};
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gpio3: gpio@40400060 {
82+
compatible = "renesas,ra8-gpio";
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reg = <0x40400060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpio4: gpio@40400080 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400080 0x20>;
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port = <4>;
95+
gpio-controller;
96+
#gpio-cells = <2>;
97+
ngpios = <16>;
98+
status = "disabled";
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};
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gpio5: gpio@404000a0 {
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compatible = "renesas,ra8-gpio";
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reg = <0x404000a0 0x20>;
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port = <5>;
105+
gpio-controller;
106+
#gpio-cells = <2>;
107+
ngpios = <16>;
108+
status = "disabled";
109+
};
110+
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gpio6: gpio@404000c0 {
112+
compatible = "renesas,ra8-gpio";
113+
reg = <0x404000c0 0x20>;
114+
port = <6>;
115+
gpio-controller;
116+
#gpio-cells = <2>;
117+
ngpios = <16>;
118+
status = "disabled";
119+
};
120+
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gpio7: gpio@404000e0 {
122+
compatible = "renesas,ra8-gpio";
123+
reg = <0x404000e0 0x20>;
124+
port = <7>;
125+
gpio-controller;
126+
#gpio-cells = <2>;
127+
ngpios = <16>;
128+
status = "disabled";
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};
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gpio8: gpio@40400100 {
132+
compatible = "renesas,ra8-gpio";
133+
reg = <0x40400100 0x20>;
134+
port = <8>;
135+
gpio-controller;
136+
#gpio-cells = <2>;
137+
ngpios = <16>;
138+
status = "disabled";
139+
};
140+
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gpio9: gpio@40400120 {
142+
compatible = "renesas,ra8-gpio";
143+
reg = <0x40400120 0x20>;
144+
port = <9>;
145+
gpio-controller;
146+
#gpio-cells = <2>;
147+
ngpios = <16>;
148+
status = "disabled";
149+
};
150+
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gpioa: gpio@40400140 {
152+
compatible = "renesas,ra8-gpio";
153+
reg = <0x40400140 0x20>;
154+
port = <10>;
155+
gpio-controller;
156+
#gpio-cells = <2>;
157+
ngpios = <16>;
158+
status = "disabled";
159+
};
160+
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gpiob: gpio@40400160 {
162+
compatible = "renesas,ra8-gpio";
163+
reg = <0x40400160 0x20>;
164+
port = <11>;
165+
gpio-controller;
166+
#gpio-cells = <2>;
167+
ngpios = <16>;
168+
status = "disabled";
169+
};
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};
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&nvic {

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