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Starting working on Python script for automatic HLS project generation.
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‎README.md‎

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@@ -12,13 +12,14 @@ The approximation algorithms are in the `python/` folder.
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* CMake
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* Xilinx Vivado 2018.3 (deprecated)
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* Xilinx Vitis 2021.1 (deprecated)
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* Xilinx Vitis 2021.1
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### CMake Simulation
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In order to make CMake include the HLS header libraries, one must modify the file `FindVitis.cmake` under `cmake/Modules`.
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#### Windows
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Simulation is working assuming the Xilinx OpenCV DLLs are copied into the `bin/` folder along side with the generated executables.
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```
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"C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64
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mkdir build
@@ -31,7 +32,7 @@ cmake --build . --config Release
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mkdir build
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cd build
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cmake ..
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make all
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make -j 4 all
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```
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## Notes on Using Vitis HLS
@@ -50,7 +51,7 @@ Note: for using external DMAs, we need the TLAST, TKEEP and TSTRB signals. In pa
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This repository contains a wrapper class for kernel arguments of type `hls::stream` named `AxiStreamInterface`. The class is implemented following a _Policy-based_ C++ paradigm, meaning that it accepts either a `AxiStreamPort` or `AxiStreamFifo` as possible policies (in practice, a template argument).
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The idea is to have a kernel argument, i.e. an HLS port, which can be either an AXIS interface with side-channels, or a bare FIFO interface connected to another kernel. In fact, Vitis HLS doesn't allow stream interfaces with side-channels within an IP. To overcome the issue, the `AxiStreamInterface` can be customized to be an IP port or a FIFO port, depending on the use of the kernel.
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The idea is to have a kernel argument, i.e. an HLS port, which can be either an AXIS interface with side-channels, or a bare FIFO interface connected to another kernel. In fact, Vitis HLS doesn't allow stream interfaces with side-channels *within* an IP. To overcome this issue, the `AxiStreamInterface` can be customized to be an IP port or a FIFO port, depending on the use of the kernel.
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An example of this can be seen in `HlsKernelU` and in `svd::SvdKernel`, which specialize the `svd::KernelU` function template. In the first case, the `svd::KernelU` has its output stream port `xu_port` connected to one of the IP's ports (with side-channels). In the latter case instead, `svd::KernelU` is connected to `svd::KernelS`, and so its `xu_port` argument is an internal FIFO (without side-channels).
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@@ -73,8 +74,8 @@ The type `ap_axiu` must now be used to generate AXIS with side channels.
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### hls::vector Arrays on AXI-Lite Interfaces
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In Vitis 2021.1 it **not** allowed to have `hls::vector` type arguments mapped to AXI-Lite interfaces.
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Instead, use a bare arrays, *e.g.* `const int x[N]` instead of `const hls::vector<int, N> x`.
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In Vitis 2021.1 it is **not** allowed to have `hls::vector` type arguments mapped to AXI-Lite interfaces.
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Instead, use bare arrays, *e.g.* `const int x[N]` instead of `const hls::vector<int, N> x`.
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### Partitioning hls::vector Arrays
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‎include/layers/lstm/lstm_data_handler.h‎

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@@ -668,7 +668,9 @@ class AcceleratorBlob {
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for (int i = 0; i < this->lstm_num_inputs_; ++i) {
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for (int j = 0; j < this->lstm_output_size_; ++j) {
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if (verbose > 0) {
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std:: cout << j << ") hls/emulator: " << this->fix_h_curr_[i][j] << " / " << x[i][j];
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auto h_tmp = this->fix_h_curr_[i][j];
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auto x_tmp = x[i][j];
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std:: cout << j << ") hls/emulator: " << h_tmp << " / " << x_tmp;
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}
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if (this->fix_h_curr_[i][j] != x[i][j]) {
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++num_errors;

‎make_hls.py‎

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import os
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import argparse
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import re
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def get_tcl_utils():
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utils = '''#
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# @brief Greps a file content and writes matches to a file.
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#
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# @param re Regular expression
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# @param lines Number of lines to report/include after the found match
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# @param fin The fin pointer
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# @param fout The fout pointer
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#
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proc grep {re lines fin write_fout fout} {
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set cnt 0
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set match false
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seek $fin 0
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while {[gets $fin line] >= 0} {
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if [regexp -- $re $line] {
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set cnt 0
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set match true
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}
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if {$match && ($cnt < $lines)} {
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puts $line
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if {$write_fout} {
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puts $fout $line
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}
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set cnt [expr {$cnt +1}]
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} else {
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set match false
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}
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}
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}
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'''
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return utils
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def is_top_file(filename, top):
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found = False
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with open(filename, 'r') as f:
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for line in f:
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if top in line:
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found = True
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break
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return found
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def get_dependent_files(filename):
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headers = []
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with open(filename, 'r') as f:
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for line in f:
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if '#include' in line:
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headers.append(line)
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return headers
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def main():
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avail_fpgas = {
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'ZedBoard' : 'xc7z020clg484-1',
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'ZCU104' : 'xczu7ev-ffvc1156-2-e',
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'ZCU102' : 'xczu9eg-ffvb1156-2-i',
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'Arty-7' : 'xc7a100tcsg324-1'
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}
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parser = argparse.ArgumentParser(description='Generate a TCL script file for HLS projects generation.')
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parser.add_argument('top', metavar='top', type=str, help='The top HLS function name.')
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parser.add_argument('--top_file', type=str, default='', help='The filename of the top HLS function. Default: None.')
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parser.add_argument('--script_name', type=str, default='run_hls_test.tcl', help='Generated TCL filename. Default: run_hls.tcl.')
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parser.add_argument('--run_hls', action='store_true', help='Run th generated TCL file. Default: False.')
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parser.add_argument('--board', type=str, choices=avail_fpgas.keys(), default='ZedBoard', help='The target FPGA board.')
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parser.add_argument('--period', type=str, default='10', help='Clock period in ns. Default: 10.')
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# Actions
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parser.add_argument('--use_vivado_hls', action='store_true', help='Use Vivado HLS. Default is Vitis HLS.')
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parser.add_argument('--no_synthesis', action='store_true', help='Do not run synthesis.')
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parser.add_argument('--csim', action='store_true', help='Run C/C++ simulation.')
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parser.add_argument('--cosim', action='store_true', help='Run C/C++ co-simulation.')
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parser.add_argument('--export', action='store_true', help='Export IP.')
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parser.add_argument('--place_and_route', action='store_true', help='Export IP and check place-and-route.')
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parser.add_argument('--no_reset_prj', action='store_true', help='Do not reset HLS project.')
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parser.add_argument('--debug_dataflow', action='store_true', help='Resize FIFO depths for dataflow check.')
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parser.add_argument('--profile_dataflow', action='store_true', help='Resize FIFO depths for dataflow check.')
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parser.add_argument('--resize_fifos', action='store_true', help='Resize FIFO depths for dataflow check.')
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parser.add_argument('--scheduler_effort', type=str, choices=['low', 'medium', 'high'], default='high', help='The HLS scheduler effort. Default: high.')
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parser.add_argument('--tb_dir', type=str, default='testbenches', help='Testbench dir name under src files. Default: testbenches.')
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parser.add_argument('--tb_file', type=str, default='', help='Testbench file name under tb_dir. Default: None.')
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parser.add_argument('--cc', type=str, choices=['11', '14'], default='14', help='The target C++ version. Default: C++14.')
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parser.add_argument('--cflags', type=str, default='-O3 -std=c++14', help='C++ cflags. Default: -O3 -std=c++14.')
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parser.add_argument('--ldflags', type=str, default='', help='C++ linker flags. Default: None.')
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parser.add_argument('--argv', type=str, default='', help='The simulation and co-simulation arguments.')
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parser.add_argument('--src', type=str, default='src', help='The C/C++ source directory. Default: src.')
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parser.add_argument('--include', type=str, default='include', help='The C/C++ include directory. Default: include.')
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parser.add_argument('--defines', type=str, default='', help='The C/C++ defines. Default: None.')
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parser.add_argument('--defines_file', type=str, default='', help='The file containing all C/C++ defines. Default: None.')
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98+
args = parser.parse_args()
99+
100+
if args.csim and args.tb_file == '' or args.cosim and args.tb_file == '':
101+
parser.error('The --csim and --cosim arguments requires --tb_file.')
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103+
print(args)
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curr_dir = os.getcwd().replace('\\', '/') + '/'
106+
hls_prj_dir = curr_dir + '/hls_prj/'
107+
hls_report_dir = hls_prj_dir + '/reports'
108+
hls_tool = 'vhls' if args.use_vivado_hls else 'vitis'
109+
prj_name = f'{hls_tool}_{args.board}_{args.top}'
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111+
cflags = args.cflags + ' -I' + curr_dir + args.include
112+
if hls_tool == 'vhls':
113+
cflags = '-fno-builtin ' + cflags.replace('c++14', 'c++0x')
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print(f'[WARNING] Replacing C++14 with C++11 in Vivado HLS. CFLAGS: {cflags}')
115+
116+
with open(args.script_name, 'w') as f:
117+
f.write(get_tcl_utils())
118+
f.write(f'exec mkdir -p -- {hls_prj_dir}\n')
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f.write(f'exec mkdir -p -- {hls_report_dir}\n')
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f.write(f'cd {hls_prj_dir}\n')
121+
f.write('open_project {} "{}"\n'.format('-reset' if not args.no_reset_prj else '', prj_name))
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f.write(f'set_top "{args.top}"\n')
123+
if not args.no_reset_prj:
124+
pass
125+
if args.csim or args.cosim:
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pass
127+
if hls_tool == 'vitis':
128+
f.write(f'open_solution -flow_target vivado -reset "{args.top}"\n')
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else:
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f.write(f'open_solution "{args.top}"\n')
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if not args.no_reset_prj:
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f.write(f'set_part {avail_fpgas[args.board]} ;# {args.board}\n')
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f.write(f'create_clock -period {args.period} -name default\n')
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if hls_tool == 'vitis':
135+
f.write(f'config_compile -name_max_length=12 -pipeline_style=frp -enable_auto_rewind=1\n')
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else:
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f.write(f'config_compile -name_max_length=12\n')
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f.write(f'config_schedule -effort={args.scheduler_effort} -relax_ii_for_timing=0\n')
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f.write(f'config_core DSP48 -latency 3\n')
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# TODO: Recursively include only the files from which the top function depends on.
142+
headers = []
143+
if args.top_file:
144+
for fpath, subdirs, files in os.walk(args.src):
145+
for fname in files:
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if args.top_file.replace('.cpp', '') == fname.replace('.cpp', '') or \
147+
args.top_file.replace('.h', '') == fname.replace('.h', ''):
148+
headers_decl = get_dependent_files(fpath + '/' + fname)
149+
for h in headers_decl:
150+
match = re.search('"(.*?)"', h)
151+
if match is not None:
152+
for m in match.groups():
153+
headers.append(m.replace('"', ''))
154+
match = re.search('<(.*?)>', h)
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if match is not None:
156+
for m in match.groups():
157+
tmp = m.replace('<', '')
158+
tmp = tmp.replace('>', '')
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headers.append(tmp)
160+
print(headers)
161+
162+
f.write(f'# Source files\n')
163+
for fpath, subdirs, files in os.walk(args.src):
164+
for fname in files:
165+
unix_filename = curr_dir + '/' + fpath.replace('\\', '/') + '/' + fname
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if fname.endswith('.cpp') or fname.endswith('.cc'):
167+
if args.tb_dir.replace('\\', '/') not in fpath:
168+
print(f'[INFO] Adding synthesis file: {unix_filename}')
169+
f.write(f'add_files {unix_filename} -cflags "{cflags}"\n')
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else:
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if fname.startswith(args.tb_file):
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print(f'[INFO] Adding simulation file: {unix_filename}')
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f.write(f'add_files -tb {unix_filename} -cflags "{cflags}"\n')
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f.write(f'# Include files\n')
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for fpath, subdirs, files in os.walk(args.include):
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for fname in files:
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unix_filename = curr_dir + '/' + fpath.replace('\\', '/') + '/' + fname
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if fname.endswith('.h'):
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if args.tb_dir.replace('\\', '/') not in fpath:
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print(f'[INFO] Adding synthesis file: {unix_filename}')
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f.write(f'add_files {unix_filename} -cflags "{cflags}"\n')
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else:
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if fname.startswith(args.tb_file):
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print(f'[INFO] Adding simulation file: {unix_filename}')
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f.write(f'add_files -tb {unix_filename} -cflags "{cflags}"\n')
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if args.csim:
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f.write(f'csim_design -clean -O -ldflags {args.ldflags} -argv {args.argv}\n')
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if not args.no_synthesis:
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f.write(f'csynth_design\n')
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csynth_report = hls_prj_dir + prj_name + f'/solution_{args.top}/syn/report/{args.top}_csynth.rpt'
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report_outfile = hls_report_dir + f'/{hls_tool}_{args.board}_{args.top}.rpt'
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report_info = f'''puts "================================================================"
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puts "\[INFO\] Reporting information"
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puts "================================================================"
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set fin [open {csynth_report} r]
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set fout [open {report_outfile} a]
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grep "== Performance Estimates" 18 $fin 0 $fout
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grep "== Utilization Estimates" 20 $fin 0 $fout
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close $fin
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close $fout'''
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f.write(f'{report_info}\n')
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if args.cosim:
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cosim_cmd = f'cosim_design -trace_level port -ldflags "{args.ldflags}" -argv "{args.argv}"'
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if hls_tool == 'vitis' and args.debug_dataflow:
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cosim_cmd += ' -enable_dataflow_profiling=1 -enable_fifo_sizing=1'
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f.write(f'{cosim_cmd}\n')
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cosim_report = hls_prj_dir + prj_name + f'/solution_{args.top}/syn/report/{args.top}_cosim.rpt'
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report_info = f'''puts "================================================================"
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puts "\[INFO\] Reporting information"
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puts "================================================================"
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set fin [open {csynth_report} r]
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set fout [open {report_outfile} a]
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grep "Simulation tool" 10 $fin 0 $fout
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close $fin
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close $fout'''
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f.write(f'{report_info}\n')
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if args.export:
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f.write('export_design -format ip_catalog\n')
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if args.place_and_route:
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f.write('export_design -flow impl -rtl verilog -format ip_catalog\n')
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closing = f'''puts "================================================================"
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puts "\[INFO\] Closing project: {prj_name}"
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puts "================================================================"
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exit
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cd {curr_dir}'''
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f.write(f'{closing}\n')
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if args.run_hls:
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if hls_tool == 'vhls':
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os.system(f'vivado_hls -f {args.script_name}')
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else:
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os.system(f'D:/Programs/Xilinx/Vitis_HLS/2021.1/bin/vitis_hls -f {args.script_name}')
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if __name__ == '__main__':
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main()

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