forked from openhwgroup/core-v-mcu
-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathMakefile
More file actions
executable file
·132 lines (110 loc) · 5.15 KB
/
Makefile
File metadata and controls
executable file
·132 lines (110 loc) · 5.15 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
# Copyright 2021 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
YML=$(shell find . -name '*.yml' -print)
IOSCRIPT=rtl/includes/pulp_soc_defines.sv
IOSCRIPT+=rtl/includes/pulp_peripheral_defines.svh
IOSCRIPT+=rtl/includes/periph_bus_defines.svh
IOSCRIPT+=pin-table.csv
IOSCRIPT+=perdef.json
#IOSCRIPT+=emulation/core-v-mcu-nexys/rtl/core_v_mcu_nexys.v
IOSCRIPT+=emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc
IOSCRIPT_OUT=rtl/core-v-mcu/top/pad_control.sv
#IOSCRIPT_OUT+=rtl/core-v-mcu/top/pad_frame.sv
IOSCRIPT_OUT+=rtl/includes/pulp_peripheral_defines.svh
IOSCRIPT_OUT+=rtl/includes/periph_bus_defines.svh
IOSCRIPT_OUT+=emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
IOSCRIPT_OUT+=core-v-mcu-config.h
#Must also change the localparam 'L2_BANK_SIZE' in pulp_soc.sv accordingly
export INTERLEAVED_BANK_SIZE=28672
#Must also change the localparam 'L2_BANK_SIZE_PRI' in pulp_soc.sv accordingly
export PRIVATE_BANK_SIZE=8192
help:
@echo "all: create generated src files, doc and sw header files"
@echo "src: create generated src files"
@echo "lint: run Verilator lint check"
@echo "doc: generate documentation"
@echo "sw: generate C header files (in ./sw)"
@echo "nexys-emul: generate bitstream for Nexys-A7-100T emulation)"
@echo "buildsim: build for Questa sim"
@echo "sim: run Questa sim"
@echo "clean: remove generated files"
all: ${IOSCRIPT_OUT} docs sw
src: ${IOSCRIPT_OUT}
clean:
(cd docs; make clean)
(cd sw; make clean)
.PHONY: model-lib
model-lib:
fusesoc --cores-root . run --target=model-lib --setup \
--build openhwgroup.org:systems:core-v-mcu | tee model-lib.log
lint:
fusesoc --cores-root . run --target=lint --setup --build openhwgroup.org:systems:core-v-mcu 2>&1 | tee lint.log
.PHONY:sim
sim:
ln -f tb/wave.do build/openhwgroup.org_systems_core-v-mcu_0/sim-modelsim/wave.do
(cd build/openhwgroup.org_systems_core-v-mcu_0/sim-modelsim; make run-gui) 2>&1 | tee sim.log
.PHONY:buildsim
buildsim:
(cd tb/uartdpi; cc -shared -Bsymbolic -fPIC -o uartdpi.so -lutil uartdpi.c)
fusesoc --cores-root . run --no-export --target=sim --setup --build openhwgroup.org:systems:core-v-mcu 2>&1 | tee buildsim.log
nexys-emul: ${IOSCRIPT_OUT}
@echo "*************************************"
@echo "* *"
@echo "* setting up nexys specific files *"
@echo "* *"
@echo "*************************************"
mkdir -p emulation/core-v-mcu-nexys/rtl
python3 util/ioscript.py\
--soc-defines rtl/includes/pulp_soc_defines.sv\
--peripheral-defines rtl/includes/pulp_peripheral_defines.svh\
--pin-table pin-table.csv\
--perdef-json perdef.json\
--emulation-toplevel core_v_mcu_nexys\
--xilinx-core-v-mcu-sv emulation/core-v-mcu-nexys/rtl/core_v_mcu_nexys.v\
--input-xdc emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc\
--output-xdc emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
@echo "*************************************"
@echo "* *"
@echo "* running Vivado *"
@echo "* *"
@echo "*************************************"
(\
export BOARD=nexys;\
export BOARD_CLOCK_MHZ=100;\
export XILINX_PART=xc7a100tcsg324-1;\
export XILINX_BOARD=digilentinc.com:nexys-a7-100t:1.0;\
export FC_CLK_PERIOD_NS=100;\
export PER_CLK_PERIOD_NS=200;\
export FPGA_CLK_PERIOD_NS=125;\
export SLOW_CLK_PERIOD_NS=30517;\
fusesoc --cores-root . run --target=nexys-a7-100t --setup --build openhwgroup.org:systems:core-v-mcu\
) 2>&1 | tee lint.log
cp ./build/openhwgroup.org_systems_core-v-mcu_0/nexys-a7-100t-vivado/openhwgroup.org_systems_core-v-mcu_0.runs/impl_1/core_v_mcu_nexys.bit emulation/core_v_mcu_nexys.bit
.PHONY:docs
docs:
(cd docs; make)
.PHONY:sw
sw:
(cd sw; make)
${IOSCRIPT_OUT}: ${IOSCRIPT}
python3 util/ioscript.py\
--soc-defines rtl/includes/pulp_soc_defines.sv\
--peripheral-defines rtl/includes/pulp_peripheral_defines.svh\
--periph-bus-defines rtl/includes/periph_bus_defines.svh\
--pin-table pin-table.csv\
--perdef-json perdef.json\
--pad-control rtl/core-v-mcu/top/pad_control.sv\
--xilinx-core-v-mcu-sv emulation/core-v-mcu-nexys/rtl/core_v_mcu_nexys.v\
--input-xdc emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc\
--output-xdc emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
.PHONY:bitstream
bitstream: ${SCRIPTS} ${IOSCRIPT_OUT}
(cd fpga; make nexys rev=nexysA7-100T) 2>&1 | tee vivado.log
download0:
vivado -mode batch -source emulation/core-v-mcu-nexys/tcl/download_bitstream.tcl -tclargs\
emulation/core_v_mcu_nexys.bit
download:
vivado -mode batch -source emulation/core-v-mcu-nexys/tcl/download_bitstream1.tcl -tclargs\
emulation/core_v_mcu_nexys.bit
(cd build/openhwgroup.org_systems_core-v-mcu_0/sim-modelsim; make run) 2>&1 | tee sim.log