Zihintntl Extension Sail Support

[jjscheel]

Technical Group

Unprivileged Spec IC

ratification-pkg

Zihintntl

Technical Liaison

Prashanth Mundkur

Task Category

SAIL model

Task Sub Category

• gcc
• binutils
• gdb
• intrinsics
• Java
• KVM
• ld
• llvm
• Linux kernel
• QEMU
• Spike

Ratification Target

Already Ratified

spec-link

https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view

Statement of Work (SOW)

Component names:
RISC-V Sail Model

Requirements:
The NTL instructions are HINTs that indicate that the explicit memory accesses of the immediately
subsequent instruction (henceforth "target instruction") exhibit poor temporal locality of reference.
The NTL instructions do not change architectural state, nor do they alter the architecturally visible
effects of the target instruction.

Sail support for this hint has not yet been created. This SOW delivers extension support for the Zihintntl in the Sail model, including command line configuration and build verification tests.

See Chapter 9 "'Zihintntl' Extension for Non-Temporal Locality Hints, Version 1.0" in the The RISC-V Instruction Set: Manual Volume I specification for details about the extension.

NOTE: Per the comment in Issue #45, Zihintpause Extension Sail Support from Jordan Carlin below, this work should wait until the new module system (riscv/sail-riscv#572) is merged to that it will simplify the overriding of existing encoding. It should also wait for the Zicbop Sail PR #538 to demonstrate the enablement technique.

Deliverables:

• RISC-V Sail model changes accepted into community for extension
• RISC-V Sail model build verification tests written for extension and accepted into community

Acceptance Criteria:

• PR(s) reviewed and accepted
• Build verification tests passing
• Passes any tests created in Architecture Compatibility Tests

SOW Signoffs: (delete those not needed)

• Task group liaison sign-off
• Development partner sign-off
• Golden Model SIG sign-off (if SAIL work)

Waiver

• Freeze
• Ratification

Pull Request Details

No response

[jjscheel]

@pmundkur, @gsterlin, please review and provide feedback on this draft SOW.

[gsterlin]

@jjscheel looks good to me. Besides sign offs, is there anything else we need to track for accountability?

[jjscheel]

No, signoff don't occur until after EVERYTHING is done (work merged). Now we wait for pre-requisite work to complete before we assign it.

[pmundkur]

As with #45 the main pre-requisite is riscv/sail-riscv#572. Hopefully we should be quite close to getting that updated and merged soon.

[jordancarlin]

The module system (riscv/sail-riscv#572) has been merged, so it should be possible to start on this now.

[pmundkur]

PR submitted: riscv/sail-riscv#1208

[pmundkur]

The PR got merged, and this task is now complete.