Commit 4f6d000
committed
Bump Spike and pk to latest commits
1 parent 935b263 commit 4f6d000
2 files changed
+2
-2
lines changed- README.md+4-1
- configure+2.1k-1.3k
- machine/emulation.c+58
- machine/emulation.h+1
- machine/encoding.h+3.2k-12.7k
- machine/machine.mk.in+1
- machine/mentry.S+20-17
- machine/minit.c+8-3
- machine/misaligned_ldst.c+24-3
- machine/misaligned_vec_ldst.c+140
- machine/mtrap.h+1
- pk/elf.c+13-8
- pk/handlers.c+19
- pk/mmap.c+5-9
- pk/pk.c+31-1
- pk/syscall.c+138
- pk/syscall.h+2
- scripts/config.sub+4-1
- Makefile.in+9
- README.md+16-2
- ci-tests/build-spike+1-1
- ci-tests/test-spike+5-2
- ci-tests/testlib.cc
- config.h.in-6
- configure-33
- configure.ac+1-1
- disasm/disasm.cc+50-21
- disasm/isa_parser.cc+38-10
- fdt/libfdt.h+2-2
- fesvr/byteorder.h+6-12
- fesvr/elfloader.h+1
- fesvr/htif_pthread.h+1-1
- riscv/cfg.cc+5-2
- riscv/csr_init.cc+383
- riscv/csrs.cc+103-25
- riscv/csrs.h+18-5
- riscv/debug_module.cc+2-2
- riscv/decode_macros.h+12-8
- riscv/dts.cc+106-50
- riscv/dts.h+5-6
- riscv/encoding.h+17-2
- riscv/entropy_source.h+5
- riscv/execute.cc+33-10
- riscv/insn_template.cc+23-24
- riscv/insns/c_ld.h+1-1
- riscv/insns/c_ldsp.h+1-1
- riscv/insns/c_sd.h+1-1
- riscv/insns/c_sdsp.h+1-1
- riscv/insns/dret.h+9-1
- riscv/insns/fcvtmod_w_d.h+1-2
- riscv/insns/jal.h+1
- riscv/insns/jalr.h+1
- riscv/insns/mret.h+2-1
- riscv/insns/sret.h+9
- riscv/insns/vcompress_vm.h+5-4
- riscv/insns/vnclip_wi.h+3-3
- riscv/insns/vnclip_wv.h+3-3
- riscv/insns/vnclip_wx.h+3-3
- riscv/insns/vnclipu_wi.h+3-3
- riscv/insns/vnclipu_wv.h+3-3
- riscv/insns/vnclipu_wx.h+3-3
- riscv/insns/vsmul_vv.h+4-4
- riscv/insns/vsmul_vx.h+4-4
- riscv/insns/vssra_vi.h+1-1
- riscv/insns/vssra_vv.h+1-1
- riscv/insns/vssra_vx.h+1-1
- riscv/insns/vssrl_vi.h+1-1
- riscv/insns/vssrl_vv.h+1-1
- riscv/insns/vssrl_vx.h+1-1
- riscv/interactive.cc+8-11
- riscv/isa_parser.h+5-1
- riscv/log_file.h+1-1
- riscv/mmu.cc+88-32
- riscv/mmu.h+22-30
- riscv/platform.h+2
- riscv/plic.cc+1-1
- riscv/processor.cc+46-424
- riscv/processor.h+15-8
- riscv/riscv.ac-12
- riscv/riscv.mk.in+1
- riscv/sim.cc+60-45
- riscv/sim.h-1
- riscv/triggers.cc+70-31
- riscv/triggers.h+2-2
- riscv/v_ext_macros.h+10-10
- riscv/vector_unit.cc+8-8
- softfloat/f64_to_bf16.c+39-7
- softfloat/softfloat.mk.in-5
- spike_dasm/spike-dasm.cc+1-1
- spike_main/spike-log-parser.cc+2-2
- spike_main/spike.cc+31-42
0 commit comments