OpenOCD incorrectly attempts to write to read-only vector CSRs (vl, vtype, vlenb)

[nadime15]

So I noticed on one of my debug sessions that OpenOCD is trying to write to read-only vector CSRs during register examination and vector register access, which violates (I think, I am not sure if a debugger can or should try writing read-only registers) the RISC-V Vector specification and causes my simulation to fail.

See the following logs:

Debug: 12742 14410 riscv-013.c:748 riscv013_execute_abstract_command(): [riscv.cpu] access register=0x320c22 {regno=0xc22 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=64bit}
Debug: 12743 14410 batch.c:291 riscv_batch_run_from(): [riscv.cpu] Running batch of scans [0, 3)
Debug: 12744 14410 batch.c:255 log_batch(): 41b w 00320c22 @17 -> + 00000000 @00; 3i
Debug: 12745 14410 batch.c:199 log_dmi_decoded(): write: command=0x320c22 {control=0x320c22}
Debug: 12746 14410 batch.c:255 log_batch(): 41b r 00000000 @16 -> + 00320c22 @17; 0i
Debug: 12747 14410 batch.c:255 log_batch(): 41b - 00000000 @00 -> + 1000080c @16; 0i

According to the RISC-V Vector spec, the following CSRs are read-only (URO):

vl (0xC20) - Vector length
vtype (0xC21) - Vector data type register
vlenb (0xC22) - VLEN/8 (vector register length in bytes)

These registers can only be modified via the vsetvl, vsetvli, or vsetivli instructions, not through direct CSR writes. I’m not familiar with the riscv-openocd code, but I don’t understand the rationale for changing vlenb at runtime, since it’s meant to represent a design-time constant (with VLEN being fixed).

Modifying vl/vtype should only occur through vsetvl and related instructions using the program buffer. This might be something that needs a fix?

[TommyMurphyTM1234]

Could this be related to this existing open issue?

• Functions csr_read_progbuf() et al. should exit early if there is no program buffer #1264

As ever, capturing/zipping/attaching the full verbose OpenOCD log would be useful and might clarify.

[en-sc]

@nadime15, I'm afraid the snippet you have posted is a read, not a write, as indicated by write=arg0 of

Debug: 12742 14410 riscv-013.c:748 riscv013_execute_abstract_command(): [riscv.cpu] access register=0x320c22 {regno=0xc22 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=64bit}

Please, see [3.7.1.1. Access Register] of the RISC-V Debug Spec, in particular write field description:

When transfer is set:
0 (arg0): Copy data from the specified register into arg0 portion of data.
1 (register): Copy data from arg0 portion of data into the specified
register

Am I missing something?

[nadime15]

Yes I noticed this too yesterday but for some reason my simulation receives a write (even though the OpenOCD logs show a read). It might be on my end. I was working for weeks with upstream OpenOCD and just switched to riscv-openocd two days ago and never encountered this behavior. I will let you know as soon as possible, thanks!