Fix cases that “ruff --check” can't handle

Author: trdthg

riscv-ctg/docs/source/conf.py

@@ -17,6 +17,8 @@
 import os
 import re
 
+import sphinx_rtd_theme
+
 def get_version():
     changelog = open('../../CHANGELOG.md','r').read()
     x = re.findall(r'## \[(.*?)\] -',changelog)[0]
@@ -107,13 +109,11 @@ def setup(app):
 #
 #html_theme = 'bootstrap'
 #html_theme = 'alabaster'
-import sphinx_rtd_theme
 html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
 html_theme = 'sphinx_rtd_theme'
 html_theme_options = {
         'prev_next_buttons_location': 'both',
         'display_version': True,
-        'includehidden': False,
         'collapse_navigation':True,
         'sticky_navigation': True,
         'navigation_depth': 4,

riscv-ctg/riscv_ctg/constants.py

@@ -1,9 +1,8 @@
 # See LICENSE.incore for details
 
 import os
-from math import *
+from math import sqrt
 from string import Template
-from riscv_isac.fp_dataset import *
 
 root = os.path.abspath(os.path.dirname(__file__))
 

riscv-ctg/riscv_ctg/cross_comb.py

@@ -1,15 +1,15 @@
 # See LICENSE.incore for details
 import random
-from constraint import *
+from constraint import Problem
+from string import Template
 
 import riscv_isac.utils as isac_utils
 
 import riscv_ctg.utils as utils
 import riscv_ctg.constants as const
-from riscv_ctg.constants import *
+from riscv_ctg.constants import case_template, part_template, signode_template
 from riscv_ctg.log import logger
 from riscv_ctg.generator import OPS
-from riscv_ctg.dsp_function import *
 
 INSTR_FORMAT = {
     'rformat'     : '$instr $rd, $rs1, $rs2',

riscv-ctg/riscv_ctg/csr_comb.py

@@ -3,7 +3,7 @@
 import functools
 
 from riscv_ctg.log import logger
-from riscv_ctg.constants import *
+from riscv_ctg.constants import case_template, part_template, signode_template, csr_reg_read_and_sig_upd_template, csr_reg_restore_template, csr_comb_test_template, csr_reg_write_to_field_template
 
 import tokenize as tkn
 from io import BytesIO
@@ -281,7 +281,7 @@ def csr_comb(self, cgf_node):
             try:
                 bool_expr = parse_csr_covpt(covpt)
                 sols = bool_expr.SAT()
-            except:
+            except Exception:
                 logger.error(f'Invalid csr_comb coverpoint: {covpt}')
                 continue
 
@@ -295,7 +295,8 @@ def csr_comb(self, cgf_node):
                         logger.error(f'Skipping invalid csr_comb coverpoint condition clause: {clause}')
                         continue
                     if mod is not None:
-                        if reg_with_mod is None: reg_with_mod = csr_reg
+                        if reg_with_mod is None:
+                            reg_with_mod = csr_reg
                         elif reg_with_mod != csr_reg:
                             logger.error(f'Skipping invalid csr_comb solution with modifiers on more than one registers for the coverpoint: {covpt}')
                             continue

riscv-ctg/riscv_ctg/ctg.py

@@ -13,11 +13,9 @@
 from riscv_ctg.generator import Generator
 from riscv_ctg.cross_comb import cross
 from riscv_ctg.csr_comb import GeneratorCSRComb
-from math import *
 from riscv_ctg.__init__ import __version__
 
 def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen, inxFlag):
-    iflen = 0
     if 'mnemonics' not in node and 'csr_comb' not in node:
         logger.warning("Neither mnemonics nor csr_comb node not found in covergroup: " + str(label))
         return
@@ -134,6 +132,6 @@ def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, ma
     op_template = utils.load_yamls(const.template_files)
     cgf = expand_cgf(cgf_file,xlen,flen)
     pool = mp.Pool(num_procs)
-    results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template,
+    pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template,
         randomize, out_dir, xlen, flen, inxFlag) for label,node in cgf.items()])
     pool.close()

riscv-ctg/riscv_ctg/dsp_function.py

@@ -95,10 +95,10 @@ def concat_simd_data(instr_dict, xlen, _bit_width):
     :type xlen: int
     :type bit_width: int
     '''
-    if type(_bit_width)==str:
+    if type(_bit_width) is str:
         _bit_width = eval(_bit_width)
 
-    if type(_bit_width)==tuple:
+    if type(_bit_width) is tuple:
         bit_width1, bit_width2 = _bit_width
     else:
         bit_width1, bit_width2 = _bit_width, _bit_width
@@ -167,10 +167,10 @@ def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile):
     :type p64_profile: string
 
     '''
-    if type(_bit_width)==str:
+    if type(_bit_width) is str:
         _bit_width = eval(_bit_width)
 
-    if type(_bit_width)==tuple:
+    if type(_bit_width) is tuple:
         bit_width1, bit_width2 = _bit_width
     else:
         bit_width1, bit_width2 = _bit_width, _bit_width

riscv-ctg/riscv_ctg/function_generators.py

@@ -3,74 +3,74 @@ def fr64_generator(req_val_comb):
         def condition(*argv):
             rs1_val = argv[0]
             rs2_val = argv[1]
-            rm = argv[2]
+            _rm = argv[2]
             bin_val = '{:064b}'.format(rs1_val)
-            fs1 = int(bin_val[0],2)
-            fe1 = int(bin_val[1:12],2)
-            fm1 = int(bin_val[12:],2)
+            _fs1 = int(bin_val[0],2)
+            _fe1 = int(bin_val[1:12],2)
+            _fm1 = int(bin_val[12:],2)
             bin_val = '{:064b}'.format(rs2_val)
-            fs2 = int(bin_val[0],2)
-            fe2 = int(bin_val[1:12],2)
-            fm2 = int(bin_val[12:],2)
+            _fs2 = int(bin_val[0],2)
+            _fe2 = int(bin_val[1:12],2)
+            _fm2 = int(bin_val[12:],2)
             return eval(req_val_comb)
         return condition
 
     def fr32_generator(req_val_comb):
         def condition(*argv):
             rs1_val = argv[0]
             rs2_val = argv[1]
-            rm = argv[2]
+            _rm = argv[2]
             bin_val = '{:032b}'.format(rs1_val)
-            fs1 = int(bin_val[0],2)
-            fe1 = int(bin_val[1:9],2)
-            fm1 = int(bin_val[9:],2)
+            _fs1 = int(bin_val[0],2)
+            _fe1 = int(bin_val[1:9],2)
+            _fm1 = int(bin_val[9:],2)
             bin_val = '{:032b}'.format(rs2_val)
-            fs2 = int(bin_val[0],2)
-            fe2 = int(bin_val[1:9],2)
-            fm2 = int(bin_val[9:],2)
+            _fs2 = int(bin_val[0],2)
+            _fe2 = int(bin_val[1:9],2)
+            _fm2 = int(bin_val[9:],2)
             return eval(req_val_comb)
         return condition
-        
+
     def fsr64_generator(req_val_comb):
         def condition(*argv):
             rs1_val = argv[0]
-            rm = argv[1]
+            _rm = argv[1]
             bin_val = '{:064b}'.format(rs1_val)
-            fs1 = int(bin_val[0],2)
-            fe1 = int(bin_val[1:12],2)
-            fm1 = int(bin_val[12:],2)
+            _fs1 = int(bin_val[0],2)
+            _fe1 = int(bin_val[1:12],2)
+            _fm1 = int(bin_val[12:],2)
             return eval(req_val_comb)
         return condition
 
     def fsr32_generator(req_val_comb):
         def condition(*argv):
             rs1_val = argv[0]
-            rm = argv[1]
+            _rm = argv[1]
             bin_val = '{:032b}'.format(rs1_val)
-            fs1 = int(bin_val[0],2)
-            fe1 = int(bin_val[1:9],2)
-            fm1 = int(bin_val[9:],2)
+            _fs1 = int(bin_val[0],2)
+            _fe1 = int(bin_val[1:9],2)
+            _fm1 = int(bin_val[9:],2)
             return eval(req_val_comb)
-        return condition   
-        
+        return condition
+
     def fr4_64_generator(req_val_comb):
         def condition(*argv):
             rs1_val = argv[0]
             rs2_val = argv[1]
             rs3_val = argv[2]
-            rm = argv[3]
+            _rm = argv[3]
             bin_val = '{:064b}'.format(rs1_val)
-            fs1 = int(bin_val[0],2)
-            fe1 = int(bin_val[1:12],2)
-            fm1 = int(bin_val[12:],2)
+            _fs1 = int(bin_val[0],2)
+            _fe1 = int(bin_val[1:12],2)
+            _fm1 = int(bin_val[12:],2)
             bin_val = '{:064b}'.format(rs2_val)
-            fs2 = int(bin_val[0],2)
-            fe2 = int(bin_val[1:12],2)
-            fm2 = int(bin_val[12:],2)
+            _fs2 = int(bin_val[0],2)
+            _fe2 = int(bin_val[1:12],2)
+            _fm2 = int(bin_val[12:],2)
             bin_val = '{:064b}'.format(rs3_val)
-            fs3 = int(bin_val[0],2)
-            fe3 = int(bin_val[1:12],2)
-            fm3 = int(bin_val[12:],2)
+            _fs3 = int(bin_val[0],2)
+            _fe3 = int(bin_val[1:12],2)
+            _fm3 = int(bin_val[12:],2)
             return eval(req_val_comb)
         return condition
 
@@ -79,21 +79,21 @@ def condition(*argv):
             rs1_val = argv[0]
             rs2_val = argv[1]
             rs3_val = argv[2]
-            rm = argv[3]
+            _rm = argv[3]
             bin_val = '{:032b}'.format(rs1_val)
-            fs1 = int(bin_val[0],2)
-            fe1 = int(bin_val[1:9],2)
-            fm1 = int(bin_val[9:],2)
+            _fs1 = int(bin_val[0],2)
+            _fe1 = int(bin_val[1:9],2)
+            _fm1 = int(bin_val[9:],2)
             bin_val = '{:032b}'.format(rs2_val)
-            fs2 = int(bin_val[0],2)
-            fe2 = int(bin_val[1:9],2)
-            fm2 = int(bin_val[9:],2)
+            _fs2 = int(bin_val[0],2)
+            _fe2 = int(bin_val[1:9],2)
+            _fm2 = int(bin_val[9:],2)
             bin_val = '{:032b}'.format(rs3_val)
-            fs3 = int(bin_val[0],2)
-            fe3 = int(bin_val[1:9],2)
-            fm3 = int(bin_val[9:],2)
+            _fs3 = int(bin_val[0],2)
+            _fe3 = int(bin_val[1:9],2)
+            _fm3 = int(bin_val[9:],2)
             return eval(req_val_comb)
-        return condition     
+        return condition
 
     def i_generator(req_val_comb):
         def condition(*argv):
@@ -112,12 +112,12 @@ def condition(*argv):
         if flen == 32:
             return fsr32_generator
         else:
-            return fsr64_generator    
+            return fsr64_generator
       elif fmt == 'fr4format':
         if flen == 32:
             return fr4_32_generator
         else:
-            return fr4_64_generator                   
+            return fr4_64_generator
     else:
         return i_generator
 
@@ -249,12 +249,12 @@ def condition(req_val_comb):
         if flen == 32:
             return fsr32_generator
         else:
-            return fsr64_generator    
+            return fsr64_generator
       elif fmt == 'fr4format':
         if flen == 32:
             return fr4_32_generator
         else:
-            return fr4_64_generator                   
+            return fr4_64_generator
     else:
         return i_generator