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4 | 4 | from constraint import Problem, MinConflictsSolver, AllDifferentConstraint
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5 | 5 | import re
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6 | 6 | from riscv_ctg.constants import twos, e_regset, signode_template, case_template, part_template, test_template, default_regset
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| 7 | +from riscv_ctg.constants import * # noqa: F403 |
7 | 8 | from riscv_ctg.log import logger
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8 | 9 | from riscv_ctg.helpers import nan_box, sgn_extd, merge_fields_f, ExtractException
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9 | 10 | from riscv_ctg.dsp_function import gen_pair_reg_data, concat_simd_data
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| 11 | +from riscv_ctg.dsp_function import * # noqa: F403 |
10 | 12 | from riscv_isac.InstructionObject import instructionObject
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11 | 13 | import struct
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12 | 14 | import sys
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@@ -1010,7 +1012,7 @@ def valreg(self,instr_dict):
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1010 | 1012 | else:
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1011 | 1013 | FLEN = 0
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1012 | 1014 | XLEN = max(self.opnode['xlen'])
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1013 |
| - _SIGALIGN = max(XLEN,FLEN)/8 |
| 1015 | + SIGALIGN = max(XLEN,FLEN)/8 # noqa: F841 |
1014 | 1016 | stride_sz = eval(suffix)
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1015 | 1017 | template = Template(eval(self.opnode['val']['val_template']))
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1016 | 1018 | width = self.iflen if self.is_fext else self.flen
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@@ -1135,7 +1137,7 @@ def swreg(self, instr_dict):
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1135 | 1137 | else:
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1136 | 1138 | FLEN = 0
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1137 | 1139 | XLEN = max(self.opnode['xlen'])
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1138 |
| - _SIGALIGN = max(XLEN,FLEN)/8 |
| 1140 | + SIGALIGN = max(XLEN,FLEN)/8 # noqa: F841 |
1139 | 1141 | stride_sz = eval(suffix)
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1140 | 1142 | for instr in instr_dict:
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1141 | 1143 | if 'rs1' in instr and instr['rs1'] in available_reg:
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